LC4064V-10TN100I LATTICE SEMICONDUCTOR, LC4064V-10TN100I Datasheet - Page 43
LC4064V-10TN100I
Manufacturer Part Number
LC4064V-10TN100I
Description
CPLD ispMACH® 4000V Family 64 Macro Cells 125MHz EECMOS Technology 3.3V 100-Pin TQFP
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LC4032V-75TN44C.pdf
(99 pages)
Specifications of LC4064V-10TN100I
Package
100TQFP
Family Name
ispMACH® 4000V
Maximum Propagation Delay Time
10 ns
Number Of User I/os
64
Number Of Logic Blocks/elements
36
Typical Operating Supply Voltage
3.3 V
Maximum Operating Frequency
125 MHz
Number Of Product Terms Per Macro
80
Memory Type
EEPROM
Operating Temperature
-40 to 105 °C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LC4064V-10TN100I
Manufacturer:
Lattice
Quantity:
135
Company:
Part Number:
LC4064V-10TN100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LC4064V-10TN100I
Manufacturer:
LATTICE
Quantity:
20 000
Lattice Semiconductor
ispMACH 4000V/B/C/Z Power Supply and NC Connections
VCC
VCCO0
VCCO (Bank 0)
VCCO1
VCCO (Bank 1)
GND
GND (Bank 0)
GND (Bank 1)
NC
1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with
2. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.
3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order
the bank shown.
ascending horizontally.
Signal
11, 33
12, 34
5
6
28
27
—
44-pin TQFP
2
5
12, 36
6
30
13, 37
29
—
48-pin TQFP
2
K2, A9
F3
E8
H3, C8
D3
G8
4032Z: A8, B10, E1,
E3, F8, F10, J1, K3
43
56-ball csBGA
ispMACH 4000V/B/C/Z Family Data Sheet
3
25, 40, 75, 90
13, 33, 95
45, 63, 83
1, 26, 51, 76
7, 18, 32, 96
46, 57, 68, 82
—
100-pin TQFP
1
2
32, 51, 96, 115
3, 17, 30, 41, 122
58, 67, 81, 94, 105
1, 33, 65, 97
10, 24, 40, 113, 123
49, 59, 74, 88, 104
—
128-pin TQFP
2