LC4064V-5TN100C LATTICE SEMICONDUCTOR, LC4064V-5TN100C Datasheet - Page 9

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LC4064V-5TN100C

Manufacturer Part Number
LC4064V-5TN100C
Description
CPLD ispMACH® 4000V Family 64 Macro Cells 227MHz EECMOS Technology 3.3V 100-Pin TQFP
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet

Specifications of LC4064V-5TN100C

Package
100TQFP
Family Name
ispMACH® 4000V
Maximum Propagation Delay Time
5 ns
Number Of User I/os
64
Number Of Logic Blocks/elements
36
Typical Operating Supply Voltage
3.3 V
Maximum Operating Frequency
227 MHz
Number Of Product Terms Per Macro
80
Memory Type
EEPROM
Operating Temperature
0 to 90 °C

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LC4064V-5TN100C
Manufacturer:
LATTICE
Quantity:
3 490
Part Number:
LC4064V-5TN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Output Routing Pool (ORP)
The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block.
This provides greater flexibility in determining the pinout and allows design changes to occur without affecting the
pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This
allows the OE product term to follow the macrocell output as it is switched between I/O cells. Additionally, the out-
put routing pool allows the macrocell output or true and complement forms of the 5-PT bypass signal to bypass the
output routing multiplexers and feed the I/O cell directly. The enhanced ORP of the ispMACH 4000 family consists
of the following elements:
Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each
ORP has as many ORP slices as there are I/O cells in the corresponding I/O block.
Figure 7. ORP Slice
Output Routing Multiplexers
The details of connections between the macrocells and the I/O cells vary across devices and within a device
dependent on the maximum number of I/Os available. Tables 5-9 provide the connection details.
Table 6. ORP Combinations for I/O Blocks with 8 I/Os
• Output Routing Multiplexers
• OE Routing Multiplexers
• Output Routing Pool Bypass Multiplexers
I/O Cell
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
M0, M1, M2, M3, M4, M5, M6, M7
M2, M3, M4, M5, M6, M7, M8, M9
M4, M5, M6, M7, M8, M9, M10, M11
M6, M7, M8, M9, M10, M11, M12, M13
M8, M9, M10, M11, M12, M13, M14, M15
M10, M11, M12, M13, M14, M15, M0, M1
M12, M13, M14, M15, M0, M1, M2, M3
M14, M15, M0, M1, M2, M3, M4, M5
From PTOE
5-PT Fast Path
From Macrocell
Output Routing Multiplexer
OE Routing Multiplexer
9
Available Macrocells
ispMACH 4000V/B/C/Z Family Data Sheet
ORP
Bypass
Multiplexer
OE
Output
To I/O
To I/O
Cell
Cell

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