LCMXO1200C-3TN144C LATTICE SEMICONDUCTOR, LCMXO1200C-3TN144C Datasheet - Page 93

• Manufacturer Part Number: LCMXO1200C-3TN144C
• Description: CPLD MachXO Family 600 Macro Cells 1.8V/2.5V/3.3V 144-Pin TQFP Tray
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LCMXO1200C-3TN144C

• Package: 144TQFP
• Family Name: MachXO
• Number Of Macro Cells: 600
• Maximum Propagation Delay Time: 5.1 ns
• Number Of User I/os: 113
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Ram Bits: 9420.8
• Memory Type: SRAM
• Operating Temperature: 0 to 85 °C

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November 2007
For Further Information
A variety of technical notes for the MachXO family are available on the Lattice web site.
For further information on interface standards refer to the following web sites:
• TN1091,
• TN1089,
• TN1092,
• TN1090,
• TN1086,
• TN1087,
• TN1097,
• AN8066,
• JEDEC Standards (LVTTL, LVCMOS): www.jedec.org
• PCI: www.pcisig.com
MachXO sysIO Usage Guide
MachXO sysCLOCK Design and Usage Guide
Memory Usage Guide for MachXO Devices
Power Estimation and Management for MachXO Devices
MachXO JTAG Programming and Configuration User’s Guide
Minimizing System Interruption During Configuration Using TransFR Technology
MachXO Density Migration
Boundary Scan Testability with Lattice sysIO Capability
6-1
MachXO Family Data Sheet
Supplemental Information
DS1002 Further Information_01.2
Data Sheet DS1002