M4A3-32/32-7VC LATTICE SEMICONDUCTOR, M4A3-32/32-7VC Datasheet - Page 11

• Manufacturer Part Number: M4A3-32/32-7VC
• Description: CPLD ispMACH™ 4A Family 1.25K Gates 32 Macro Cells 105MHz/125MHz EECMOS Technology 3.3V 44-Pin TQFP Tray
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of M4A3-32/32-7VC

• Package: 44TQFP
• Family Name: ispMACH™ 4A
• Device System Gates: 1250
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 32
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 105|125 MHz
• Number Of Product Terms Per Macro: 20
• Operating Temperature: 0 to 70 °C

The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The
primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality
is defined in Table 8. Note that a J-K latch is inadvisable as it will cause oscillation if both J and K inputs
are HIGH.
e. T-type with programmable T polarity
c. Latch with XOR
a. D-type with XOR
L
T
G
D
AP AR
AP AR
AP AR
Figure 6. Primary Macrocell Configurations
g. Combinatorial with programmable polarity
Q
Q
Q
ispMACH 4A Family
b. D-type with programmable D polarity
d. Latch with programmable D polarity
f. Combinatorial with XOR
D
L
G
AP AR
AP AR
Q
Q
17466G-011
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