XC2C128-7CPG132I Xilinx Inc, XC2C128-7CPG132I Datasheet - Page 7

• Manufacturer Part Number: XC2C128-7CPG132I
• Description: CPLD CoolRunner™-II Family 3K Gates 128 Macro Cells 152MHz 0.18um (CMOS) Technology 1.8V 132-Pin CSBGA
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C128-7CPG132I

• Package: 132CSBGA
• Family Name: CoolRunner™-II
• Device System Gates: 3000
• Number Of Macro Cells: 128
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 100
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 1.8 V
• Maximum Operating Frequency: 152 MHz
• Number Of Product Terms Per Macro: 40
• Operating Temperature: -40 to 85 °C
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 8
• Number Of Macrocells: 128
• Number Of Gates: 3000
• Number Of I /o: 100
• Mounting Type: Surface Mount
• Package / Case: 132-CSBGA
• Features: JTAG
• Voltage: 1.8V
• Memory Type: CMOS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC Electrical Characteristics Over Recommended Operating Conditions
DS093 (v3.2) March 8, 2007
Product Specification
Notes:
1.
2.
3.
4.
T
T
T
T
T
T
T
T
F
F
F
F
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
OE
AO
APRPW
PD1
PD2
SUD
SU1
SU2
HD
H
CO
TOGGLE
SYSTEM1
SYSTEM2
EXT1
EXT2
PSUD
PSU1
PSU2
PHD
PH
PCO
POE
MOE
PAO
SUEC
HEC
CW
PCW
DGSU
DGH
DGR
DGW
CDRSU
CDRH
CONFIG
Symbol
F
F
F
F
Typical configuration current during
/T
TOGGLE
SYSTEM1
SYSTEM2
EXT1
/T
/T
(3)
(3)
OD
POD
MOD
(4)
(1)
(1/T
(2)
(2)
R
is the maximum clock frequency to which a T flip-flop can reliably toggle (see the CoolRunner-II family data sheet).
is the internal operating frequency for a device with 16-bit resetable binary counter through one p-term per macrocell while
is through the OR array (one counter per function block).
SU1
+T
Propagation delay single p-term
Propagation delay OR array
Direct input register set-up time
Setup time fast (single p-term)
Setup time (OR array)
Direct input register hold time
Hold time (Or array or p-term)
Clock to output
Internal toggle rate
Maximum system frequency
Maximum system frequency
Maximum external frequency
Maximum external frequency
Direct input register p-term clock setup time
P-term clock setup time (single p-term)
P-term clock setup time (OR array)
Direct input register p-term clock hold time
P-term clock hold
P-term clock to output
Global OE to output enable/disable
P-term OE to output enable/disable
Macrocell driven OE to output enable/disable
P-term set/reset to output valid
Global set/reset to output valid
Register clock enable setup time
Register clock enable hold time
Global clock pulse width High or Low
Asynchronous preset/reset pulse width (High or Low)
P-term pulse width High or Low
Set-up before DataGATE latch assertion
Hold to DataGATE latch assertion
DataGATE recovery to new data
DataGATE low pulse width
CDRST setup time before falling edge GCLK2
Hold time CDRST after falling edge GCLK2
Configuration time
CO
) is the maximum external frequency using one p-term while F
T
CONFIG
Parameter
is 10 mA.
www.xilinx.com
EXT2
is through the OR array.
Min.
3.6
2.4
2.7
0.0
0.0
2.5
1.3
1.6
0.2
0.7
3.1
0.0
1.1
6.0
6.0
0.0
4.0
3.0
1.3
0.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-6
XC2C128 CoolRunner-II CPLD
Max.
450
244
227
152
145
350
5.7
6.0
4.2
5.9
5.9
7.0
7.7
6.6
5.0
8.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Min.
4.6
3.0
3.5
0.0
0.0
3.1
1.5
2.0
0.2
1.0
3.5
0.0
1.6
7.5
7.5
0.0
6.0
4.0
2.0
0.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-7
Max.
300
152
141
350
119
112
7.0
7.5
5.4
7.3
7.5
8.5
9.9
8.1
7.6
9.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Units
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
7