XC2C128-7VQ100I Xilinx Inc, XC2C128-7VQ100I Datasheet - Page 10
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XC2C128-7VQ100I
Manufacturer Part Number
XC2C128-7VQ100I
Description
CPLD CoolRunner™-II Family 3K Gates 128 Macro Cells 152MHz 0.18um (CMOS) Technology 1.8V 100-Pin VTQFP
Manufacturer
Xilinx Inc
Datasheet
1.XC2C32A-6QFG32C.pdf
(16 pages)
Specifications of XC2C128-7VQ100I
Package
100VTQFP
Family Name
CoolRunnerÂ-II
Device System Gates
3000
Number Of Macro Cells
128
Maximum Propagation Delay Time
7.5 ns
Number Of User I/os
80
Number Of Logic Blocks/elements
8
Typical Operating Supply Voltage
1.8 V
Maximum Operating Frequency
152 MHz
Number Of Product Terms Per Macro
40
Operating Temperature
-40 to 85 °C
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2C128-7VQ100I
Manufacturer:
MICROCHIP
Quantity:
3 170
Part Number:
XC2C128-7VQ100I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
CoolRunner-II CPLD Family
Design Security
Designs can be secured during programming to prevent
either accidental overwriting or pattern theft via readback.
Four independent levels of security are provided on-chip,
10
Figure 10: CoolCLOCK Created by Cascading Clock Divider and DualEDGE Option
Figure 9: Macrocell Clock Chain with DualEDGE Option Shown
Synch Reset
CLK_CT
PTC
GCK2
CTC
PTC
GCK0
GCK1
GCK2
GCK0
GCK1
GCK2
www.xilinx.com
Clock
In
Synch Rst
eliminating any electrical or visual detection of configuration
patterns. These security bits can be reset only by erasing
the entire device. See
÷10
÷12
÷14
÷16
÷2
÷4
÷6
÷8
PTC
PTC
D/T
CE
CK
D/T
CE
CK
✓
DS090_09_121201
✓
FIF
Latch
DualEDGE
FIF
Latch
DualEDGE
WP170
Q
DS090 (v3.1) September 11, 2008
Q
for more detail.
Product Specification
R