XC2C256-7PQG208C Xilinx Inc, XC2C256-7PQG208C Datasheet - Page 10

CPLD CoolRunner™-II Family 6K Gates 256 Macro Cells 152MHz 0.18um (CMOS) Technology 1.8V 208-Pin PQFP

XC2C256-7PQG208C

Manufacturer Part Number
XC2C256-7PQG208C
Description
CPLD CoolRunner™-II Family 6K Gates 256 Macro Cells 152MHz 0.18um (CMOS) Technology 1.8V 208-Pin PQFP
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Datasheets

Specifications of XC2C256-7PQG208C

Package
208PQFP
Family Name
CoolRunner™-II
Device System Gates
6000
Number Of Macro Cells
256
Maximum Propagation Delay Time
7.5 ns
Number Of User I/os
173
Number Of Logic Blocks/elements
16
Typical Operating Supply Voltage
1.8 V
Maximum Operating Frequency
152 MHz
Number Of Product Terms Per Macro
40
Operating Temperature
0 to 70 °C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.7ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
16
Number Of Macrocells
256
Number Of Gates
6000
Number Of I /o
173
Mounting Type
Surface Mount
Package / Case
208-MQFP, 208-PQFP
Features
Programmable
Voltage
1.8V
Memory Type
CMOS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1573 - KIT STARTER COOLRUNNER-II LP/LC122-1512 - KIT DESIGN CPLD W/BATT HOLDER
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1411

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC2C256-7PQG208C
Manufacturer:
PANASONIC
Quantity:
2 000
Part Number:
XC2C256-7PQG208C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC2C256-7PQG208C
Manufacturer:
XILINX
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Part Number:
XC2C256-7PQG208C
Manufacturer:
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Quantity:
20 000
CoolRunner-II CPLD Family
Design Security
Designs can be secured during programming to prevent
either accidental overwriting or pattern theft via readback.
Four independent levels of security are provided on-chip,
10
Figure 10: CoolCLOCK Created by Cascading Clock Divider and DualEDGE Option
Figure 9: Macrocell Clock Chain with DualEDGE Option Shown
Synch Reset
CLK_CT
PTC
GCK2
CTC
PTC
GCK0
GCK1
GCK2
GCK0
GCK1
GCK2
www.xilinx.com
Clock
In
Synch Rst
eliminating any electrical or visual detection of configuration
patterns. These security bits can be reset only by erasing
the entire device. See
÷10
÷12
÷14
÷16
÷2
÷4
÷6
÷8
PTC
PTC
D/T
CE
CK
D/T
CE
CK
DS090_09_121201
FIF
Latch
DualEDGE
FIF
Latch
DualEDGE
WP170
Q
DS090 (v3.1) September 11, 2008
Q
for more detail.
Product Specification
R

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