XC2C64A-7CPG56I Xilinx Inc, XC2C64A-7CPG56I Datasheet - Page 16

• Manufacturer Part Number: XC2C64A-7CPG56I
• Description: CPLD CoolRunner™-II Family 1.5K Gates 64 Macro Cells 159MHz 0.18um (CMOS) Technology 1.8V 56-Pin CSBGA
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C64A-7CPG56I

• Package: 56CSBGA
• Family Name: CoolRunner™-II
• Device System Gates: 1500
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 45
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 1.8 V
• Maximum Operating Frequency: 159 MHz
• Number Of Product Terms Per Macro: 40
• Operating Temperature: -40 to 85 °C
• Features: Programmable
• Package / Case: 56-CSBGA
• Mounting Type: Surface Mount
• Voltage: 1.8V
• Number Of I /o: 45
• Memory Type: CMOS
• Programmable Type: In System Programmable
• Number Of Macrocells: 64
• Delay Time Tpd(1) Max: 6.7ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 4
• Number Of Gates: 1500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XC2C64A CoolRunner-II CPLD
Additional Information
Additional information is available for the following
CoolRunner-II CPLD topics at
www.xilinx.com/support/documentation/coolrunner-ii.htm
•
•
Revision History
The following table shows the revision history for this document.
16
10/01/04
11/08/04
11/29/04
12/14/04
01/18/05
03/07/05
06/28/05
01/30/06
03/20/06
02/15/07
03/08/07
11/19/08
5/15/04
8/30/04
Device pinouts in the density specific data sheets
Termination, power sequencing, voltage thresholds,
and slew rate data in the CPLD IO User Guide
Date
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
Initial Xilinx release.
Pb-free documentation
Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics.
Product Release. No change to documentation.
Change to QFG package drawing (Figure 8). Pin 29 relabelled.
Changes to Figure 4, Typical I/O Output Curves; Changes to t
Timing Parameters, page 8.
Changes to I
Format change to specifications I
page 1. Modifications to Table 1, IOSTANDARDs.
Move to Product Specification. Change to T
Modified footnote 1 from AC Specifications Table to remove incorrect equation.
Add Warranty Disclaimer. Add note to Pin Descriptions that
be used for general purpose I/O.
Change to V
speed grade from 2.0 to 3.0 ns.
Fixed typo in note for V
Added note to Pin Description tables to indicate the PC44 packages are obsolete. Removed
part numbers for devices in PC44 packages the Features section and from the ordering
information. See Product Discontinuation Notice
IH
CCSB
specification for 2.5V and 1.8V LVCMOS. Change T
, f
TOGGLE
www.xilinx.com
IL
:
for LVCMOS18; removed note for V
, t
PSU1
•
•
Package drawings and dimensions are available at:
www.xilinx.com/support/documentation/package_specifications.htm
IL
, t
and I
PSU2
Reliability data in the Device Reliability Report
Packaging thermal and electrical data in the Device
Package User Guide
Revision
, t
IH
PHD
, page 3. Improvement to pin-to-pin logic delay,
IN25
, t
, T
CW
xcn07022.pdf
OUT25
, t
SLEW25
, T
IN33
GCK, GSR, and GTS pins can also
, and t
IL
DS311 (v2.3) November 19, 2008
.
OUT25
, and T
for LVCMOS33.
SLEW33
F
and t
specification on -7
OUT33
Product Specification
OUT33
.
, Internal
R