XC95108-10PQ100C Xilinx Inc, XC95108-10PQ100C Datasheet - Page 5

• Manufacturer Part Number: XC95108-10PQ100C
• Description: CPLD XC9500 Family 2.4K Gates 108 Macro Cells 66.7MHz 0.5um (CMOS) Technology 5V 100-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: XC9500r

Specifications of XC95108-10PQ100C

• Package: 100PQFP
• Family Name: XC9500
• Device System Gates: 2400
• Number Of Macro Cells: 108
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 81
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 66.7 MHz
• Number Of Product Terms Per Macro: 90
• Memory Type: Flash
• Operating Temperature: 0 to 70 °C
• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 6
• Number Of Macrocells: 108
• Number Of Gates: 2400
• Number Of I /o: 81
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Voltage: 5V
• Case: QFP100
• Dc: 01+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1178

Internal Timing Parameters
Notes:
1.
DS066 (v4.4) April 3, 2006
Product Specification
Symbol
Buffer Delays
Product Term Control Delays
Internal Register and Combinatorial Delays
Feedback Delays
Time Adders
T
T
T
T
T
T
T
T
T
T
LOGILP
T
T
T
T
T
T
PTA
T
SLEW
PTCK
PTSR
T
T
PTTS
T
LOGI
GCK
GSR
OUT
T
GTS
COI
AOI
PDI
SUI
RAI
T
EN
LF
IN
HI
F
PTA
(1)
is multiplied by the span of the function as defined in the XC9500 family data sheet.
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
Output buffer enable/disable delay
Product term clock delay
Product term set/reset delay
Product term 3-state delay
Combinatorial logic propagation delay
Register setup time
Register hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
Internal low power logic delay
FastCONNECT feedback delay
Function block local feedback delay
Incremental product term allocator delay
Slew-rate limited delay
R
Parameter
www.xilinx.com
Min
XC95108-7
1.5
3.0
7.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
10.0
2.5
1.5
4.5
5.5
2.5
3.0
2.0
4.5
0.5
0.5
6.5
2.0
8.0
4.0
1.0
4.0
0
-
-
-
XC95108-10
10.0
Min
2.5
3.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
11.0
XC95108 In-System Programmable CPLD
3.5
2.5
6.0
6.0
3.0
3.0
2.5
3.5
1.0
0.5
7.0
2.5
9.5
3.5
1.0
4.5
0
-
-
-
XC95108-15
10.0
Min
3.5
4.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
11.0
11.5
11.0
4.5
3.0
7.5
4.5
2.5
3.0
5.0
3.0
0.5
8.0
3.0
3.5
1.0
5.0
0
-
-
-
XC95108-20
10.0
Min
3.5
6.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
16.0
13.0
11.5
6.5
3.0
9.5
6.5
2.5
3.0
5.0
4.0
0.5
8.0
3.0
5.0
1.5
5.5
0
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5