XC95144-15PQ100I Xilinx Inc, XC95144-15PQ100I Datasheet - Page 5

• Manufacturer Part Number: XC95144-15PQ100I
• Description: CPLD XC9500 Family 3.2K Gates 144 Macro Cells 55.6MHz 0.5um (CMOS) Technology 5V 100-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: XC9500r

Specifications of XC95144-15PQ100I

• Package: 100PQFP
• Family Name: XC9500
• Device System Gates: 3200
• Number Of Macro Cells: 144
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 81
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 55.6 MHz
• Number Of Product Terms Per Macro: 90
• Memory Type: Flash
• Operating Temperature: -40 to 85 °C
• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.5 V ~ 5.5 V
• Number Of Logic Elements/blocks: 8
• Number Of Macrocells: 144
• Number Of Gates: 3200
• Number Of I /o: 81
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Voltage: 5V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Macrocell
Each XC9500 macrocell may be individually configured for
a combinatorial or registered function. The macrocell and
associated FB logic is shown in
Five direct product terms from the AND-array are available
for use as primary data inputs (to the OR and XOR gates) to
implement combinatorial functions, or as control inputs
including clock, set/reset, and output enable. The product
DS063 (v5.5) June 25, 2007
Product Specification
36
R
Figure
Figure 3: XC9500 Macrocell Within Function Block
Allocator
Product
Term
3.
Additional
Product
Terms
(from other
macrocells)
Additional
Product
Terms
(from other
macrocells)
Product Term Clock
Product Term Reset
Product Term Set
Product Term OE
1
0
www.xilinx.com
Set/Reset
Global
term allocator associated with each macrocell selects how
the five direct terms are used.
The macrocell register can be configured as a D-type or
T-type flip-flop, or it may be bypassed for combinatorial
operation. Each register supports both asynchronous set
and reset operations. During power-up, all user registers
are initialized to the user-defined preload state (default to 0
if unspecified).
Clocks
3
Global
XC9500 In-System Programmable CPLD Family
D/T
R
S
Q
OUT
PTOE
To
Fast CONNECTII
Switch Matrix
DS063_03_110501
To
I/O Blocks
5