LFEC10E-3FN484C LATTICE SEMICONDUCTOR, LFEC10E-3FN484C Datasheet - Page 21
LFEC10E-3FN484C
Manufacturer Part Number
LFEC10E-3FN484C
Description
FPGA LatticeEC Family 10200 Cells 340MHz 130nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC10E-3FN484C
Package
484FBGA
Family Name
LatticeEC
Device Logic Units
10200
Maximum Internal Frequency
340 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
288
Ram Bits
282624
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Lattice Semiconductor
MULTADDSUM sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/
subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction
are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-22 shows
the MULTADDSUM sysDSP element.
Figure 2-22. MULTADDSUM
Clock, Clock Enable and Reset Resources
Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset
and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3)
one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and
Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3)
at each input register, pipeline register and output register.
Multiplicand A0
Multiplicand A1
Multiplicand A2
Multiplicand A3
Multiplier B0
Multiplier B1
Multiplier B2
Multiplier B3
Shift Register B Out
Signed
Addn0
Addn1
Shift Register B In
n
n
n
n
Input Data
Register B
Input Data
Register B
Input Data
Register B
Input Data
Register B
n
n
n
n
n
n
n
n
n
Register
Register
Register
Input
Input
Input
m
m
m
m
Input Data
Register A
Input Data
Register A
Input Data
Register A
Input Data
Register A
m
m
m
m
m
Shift Register A Out
Shift Register A In
m
m
m
m
Pipeline
Register
Pipeline
Register
Pipeline
Register
m
n
n
n
m
n
m
n
2-18
Multiplier
Multiplier
Multiplier
Multiplier
To Add/Sub1
To Add/Sub0, Add/Sub1
To Add/Sub0
Register
Register
Pipeline
Pipeline
x
x
x
x
Register
Register
Pipeline
Pipeline
(default)
(default)
m+n
m+n
(default)
(default)
m+n
m+n
Add/Sub0
Add/Sub1
LatticeECP/EC Family Data Sheet
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
m+n+1
m+n+1
SUM
m+n+2
m+n+2
Architecture
Output
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