XC2S100E-6FTG256C Xilinx Inc, XC2S100E-6FTG256C Datasheet - Page 37

• Manufacturer Part Number: XC2S100E-6FTG256C
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 256-Pin FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-IIEr

Specifications of XC2S100E-6FTG256C

• Package: 256FTBGA
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 182
• Ram Bits: 40960
• Number Of Logic Elements/cells: 2700
• Number Of Labs/clbs: 600
• Total Ram Bits: 40960
• Number Of I /o: 182
• Number Of Gates: 100000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1322

IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in
Notes:
1.
DS077-3 (v2.3) June 18, 2008
Product Specification
Propagation Delays
Sequential Delays
Setup/Hold Times with Respect to Clock CLK
Set/Reset Delays
T
T
T
IOPICKD
IOICECK
IOPICK
Input timing for LVTTL is measured at 1.4V. For other I/O standards, see the table
T
Symbol
T
T
T
T
T
T
IOSRCKI
T
IOCKIQ
IOSRIQ
IOPLID
GSRQ
IOPID
IOPLI
IOB Input Delay Adjustments for Different Standards, page
IOPI
/ T
/ T
/ T
R
IOICKP
IOICKPD
IOCKICE
Pad to I output, no delay
Pad to I output, with delay
Pad to output IQ via transparent latch,
no delay
Pad to output IQ via transparent latch,
with delay
Clock CLK to output IQ
Pad, no delay
Pad, with delay
ICE input
SR input (IFF, synchronous)
SR input to IQ (asynchronous)
GSR to output IQ
Description
(1)
www.xilinx.com
Spartan-IIE FPGA Family: DC and Switching Characteristics
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
XC2S50E
XC2S50E
Device
38.
All
All
All
All
All
All
All
All
All
Delay Measurement Methodology, page
0.7 / 0.01
1.4 / 0
2.9 / 0
2.9 / 0
3.1 / 0
3.1 / 0
3.1 / 0
3.2 / 0
3.5 / 0
Min
0.4
0.5
0.7
1.3
1.3
1.3
1.3
1.3
1.4
1.5
0.1
0.9
0.5
3.8
-7
Speed Grade
Max
0.8
1.0
1.5
3.0
3.0
3.2
3.2
3.2
3.2
3.5
0.7
1.2
8.5
-
-
-
-
-
-
-
-
-
-
0.7 / 0.01
1.5 / 0
2.9 / 0
2.9 / 0
3.1 / 0
3.1 / 0
3.1 / 0
3.2 / 0
3.5 / 0
Min
0.4
0.5
0.7
1.3
1.3
1.3
1.3
1.3
1.4
1.5
0.1
1.0
0.5
3.8
-6
Max
0.8
1.0
1.6
3.1
3.1
3.3
3.3
3.3
3.4
3.7
0.7
1.4
9.7
-
-
-
-
-
-
-
-
-
-
41.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
37