XC2S100E-6TQ144I Xilinx Inc, XC2S100E-6TQ144I Datasheet - Page 17

• Manufacturer Part Number: XC2S100E-6TQ144I
• Description: FPGA Spartan®-IIE Family 100K Gates 2700 Cells 357MHz 0.15um Technology 1.8V 144-Pin TQFP
• Manufacturer: Xilinx Inc

Specifications of XC2S100E-6TQ144I

• Package: 144TQFP
• Family Name: Spartan®-IIE
• Device Logic Cells: 2700
• Device Logic Units: 600
• Device System Gates: 100000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 102
• Ram Bits: 40960

Dedicated Routing
Some classes of signal require dedicated routing resources
to maximize performance. In the Spartan-IIE FPGA archi-
tecture, dedicated routing resources are provided for two
classes of signal.
Global Routing
Global Routing resources distribute clocks and other sig-
nals with very high fanout throughout the device. Spar-
tan-IIE devices include two tiers of global routing resources
referred to as primary and secondary global routing
resources.
•
•
Clock Distribution
The Spartan-IIE family provides high-speed, low-skew clock
distribution through the primary global routing resources
described above. A typical clock distribution net is shown in
Figure
Four global buffers are provided, two at the top center of the
device and two at the bottom center. These drive the four
primary global nets that in turn drive any clock pin.
Four dedicated clock pads are provided, one adjacent to
each of the global buffers. The input to the global buffer is
DS077-2 (v2.3) June 18, 2008
Product Specification
The primary global routing resources are four
dedicated global nets with dedicated input pins that are
designed to distribute high-fanout clock signals with
minimal skew. Each global clock net can drive all CLB,
IOB, and block RAM clock pins. The primary global
nets may only be driven by global buffers. There are
four global buffers, one for each global net.
The secondary global routing resources consist of 24
backbone lines, 12 across the top of the chip and 12
across the bottom. From these lines, up to 12 unique
signals per column can be distributed via the 12
longlines in the column. These secondary resources
are more flexible than the primary resources since they
are not restricted to routing only to clock pins.
11.
CLB
R
Figure 10: BUFT Connections to Dedicated Horizontal Bus Lines
CLB
www.xilinx.com
•
•
selected either from these pads or from signals in the gen-
eral purpose routing.
Delay-Locked Loop (DLL)
Associated with each global clock input buffer is a fully digi-
tal Delay-Locked Loop (DLL) that can eliminate skew
between the clock input pad and internal clock-input pins
throughout the device. Each DLL can drive two global clock
networks. The DLL monitors the input clock and the distrib-
uted clock, and automatically adjusts a clock delay element
(Figure
edges reach internal flip-flops exactly one clock period after
they arrive at the input. This closed-loop system effectively
eliminates clock-distribution delay by ensuring that clock
CLB
Global
Clock Rows
Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are
provided per CLB row, permitting multiple busses
within a row, as shown in
Two dedicated nets per CLB propagate carry signals
vertically to the adjacent CLB.
Figure 11: Global Clock Distribution Network
Spartan-IIE FPGA Family: Functional Description
12). Additional delay is introduced such that clock
GCLKBUF1
GCLKPAD1
GCLKBUF3
GCLKPAD3
CLB
Figure
GCLKBUF0
GCLKPAD0
GCLKPAD2
GCLKBUF2
10.
DS001_08_060100
Global Clock
Column
DS001_07_090600
Global Clock
Spine
3-State
Lines
17