XC2S300E-6PQG208C Xilinx Inc, XC2S300E-6PQG208C Datasheet - Page 65
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XC2S300E-6PQG208C
Manufacturer Part Number
XC2S300E-6PQG208C
Description
FPGA Spartan®-IIE Family 300K Gates 6912 Cells 357MHz 0.15um Technology 1.8V 208-Pin PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-IIEr
Datasheet
1.XC2S50E-6TQG144C.pdf
(108 pages)
Specifications of XC2S300E-6PQG208C
Package
208PQFP
Family Name
Spartan®-IIE
Device Logic Cells
6912
Device Logic Units
1536
Device System Gates
300000
Maximum Internal Frequency
357 MHz
Typical Operating Supply Voltage
1.8 V
Maximum Number Of User I/os
146
Ram Bits
65536
Number Of Logic Elements/cells
6912
Number Of Labs/clbs
1536
Total Ram Bits
65536
Number Of I /o
146
Number Of Gates
300000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1326
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2S300E-6PQG208C
Manufacturer:
XILINX
Quantity:
292
Company:
Part Number:
XC2S300E-6PQG208C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC2S300E-6PQG208C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
DS077-4 (2.3) June 18, 2008
Product Specification
I/O, VREF
Bank 1, L6P
I/O, L6N
I/O
I/O (DLL),
L5P
GCK2, I
GND
VCCO
GCK3, I
VCCINT
I/O (DLL),
L5N
I/O, L4P
I/O, VREF
Bank 0, L4N
GND
I/O, L3P
I/O, L3N
I/O, L2P
I/O, L2N
VCCINT
VCCO
GND
I/O, L1P
I/O, L1N
I/O
Function
Pad Name
R
Bank
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
P178
P179
P180
P181
P182
P183
P184
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
P199
P200
Pin
100E, 200E,
100E, 200E,
100E, 200E,
100E, 200E,
200E, 300E
200E, 300E
200E, 300E
200E, 300E
200E, 300E
200E, 300E
XC2S50E,
XC2S50E,
XC2S50E,
XC2S50E,
XC2S50E,
XC2S50E,
XC2S50E,
XC2S50E,
XC2S50E,
XC2S50E,
Async.
Output
Option
LVDS
300E
300E
300E
300E
-
-
-
-
-
-
-
-
-
-
-
-
-
150E, 200E,
XC2S100E,
Option
300E
V
All
All
REF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
www.xilinx.com
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
PQ208 Differential Clock Pins
I/O
I/O,
L0P_YY
I/O, VREF
Bank 0,
L0N_YY
I/O
I/O
I/O
TCK
VCCO
Clock
GCK0
GCK1
GCK2
GCK3
Function
Pad Name
Bank
4
5
1
0
Bank
Spartan-IIE FPGA Family: Pinout Tables
0
0
0
0
0
0
-
-
P182
P185
P80
P77
Pin
P201
P202
P203
P204
P205
P206
P207
P208
Pin
P
GCK0, I
GCK1, I
GCK2, I
GCK3, I
Name
Async.
Output
Option
LVDS
All
All
-
-
-
-
-
-
P181
P187
P81
P75
Pin
XC2S200E,
N
I/O (DLL),
I/O (DLL),
I/O (DLL),
I/O (DLL),
Option
Name
V
300E
L31N
L31P
L5P
L5N
All
REF
-
-
-
-
-
-
65