XC2V2000-4FGG676C Xilinx Inc, XC2V2000-4FGG676C Datasheet - Page 76
![FPGA Virtex-II™ Family 2M Gates 24192 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 676-Pin FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC2V2000-4FGG676C
Manufacturer Part Number
XC2V2000-4FGG676C
Description
FPGA Virtex-II™ Family 2M Gates 24192 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 676-Pin FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-IIr
Datasheet
1.XC2V250-4FGG256C.pdf
(318 pages)
Specifications of XC2V2000-4FGG676C
Package
676FBGA
Family Name
Virtex-IIÂ
Device Logic Units
24192
Device System Gates
2000000
Number Of Registers
21504
Maximum Internal Frequency
650 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
456
Ram Bits
1032192
Number Of Labs/clbs
2688
Total Ram Bits
1032192
Number Of I /o
456
Number Of Gates
2000000
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1351
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2V2000-4FGG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Table 31: Master/Slave Serial Mode Timing Characteristics
Master/Slave SelectMAP Parameters
Figure 5
Virtex-II Pro Platform FPGA User Guide
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1.
CCLK
If no provision is made in the design to adjust the frequency of CCLK, F
is a generic timing diagram for data loading using SelectMAP. For other data loading diagrams, refer to the
Serial DOUT
R
Serial DOUT
DIN setup/hold, slave mode
DIN setup/hold, master mode
DOUT
High time
Low time
Maximum start-up frequency
Maximum frequency
Frequency tolerance, master mode with
respect to nominal
Serial DIN
Serial DIN
(Output)
CCLK
CCLK
Description
1
Figure 4: Master Serial Mode Timing Sequence
T
1
Figure 3: Slave Serial Mode Timing Sequence
DSCK
(Figure
T
DCC
(Figure
.
3)
T
4)
CKDS
2
2
T
CCD
www.xilinx.com
4
References
T
Virtex-II Platform FPGAs: DC and Switching Characteristics
CCH
Figure
1/2
1/2
3
4
5
CC_SERIAL
should not exceed F
T
F
F
T
3
DSCK
CC_STARTUP
Symbol
CC_SERIAL
DCC
T
T
T
T
CCO
CCO
CCH
CCL
/T
/T
5
CCD
CKDS
T
CCL
CC_STARTUP
5.0/0.0
5.0/0.0
Value
+45%
–30%
12.0
5.0
5.0
50
66
ds083-3_08_111104
ds083-3_09_111104
(1)
.
MHz, max
MHz, max
Module 3 of 4
ns, max
ns, min
ns, min
ns, min
ns, min
Units
28
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