XC2V250-5FG256I Xilinx Inc, XC2V250-5FG256I Datasheet - Page 61

• Manufacturer Part Number: XC2V250-5FG256I
• Description: FPGA Virtex-II™ Family 250K Gates 3456 Cells 750MHz 0.15um/0.12um (CMOS) Technology 1.5V 256-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V250-5FG256I

• Package: 256FBGA
• Family Name: Virtex-II™
• Device Logic Units: 3456
• Device System Gates: 250000
• Number Of Registers: 3072
• Maximum Internal Frequency: 750 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 172
• Ram Bits: 442368
• Number Of Labs/clbs: 384
• Total Ram Bits: 442368
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in
Table 16: IOB Output Switching Characteristics
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1. The 3-state turn-off delays should not be adjusted.
Propagation Delays
3-State Delays
Sequential Delays
Setup and Hold Times Before/After Clock CLK
Set/Reset Delays
O input to Pad
O input to Pad via transparent latch
T input to Pad high-impedance
T input to valid data on Pad
T input to Pad high-impedance via transparent latch
T input to valid data on Pad via transparent latch
GTS to Pad high impedance
Clock CLK to Pad
Clock CLK to Pad high-impedance (synchronous)
Clock CLK to valid data on Pad (synchronous)
O input
OCE input
SR input (OFF)
3–State Setup Times, T input
3–State Setup Times, TCE input
3–State Setup Times, SR input (TFF)
Minimum Pulse Width, SR input (asynchronous)
SR input to Pad (asynchronous)
SR input to Pad high-impedance (asynchronous)
SR input to valid data on Pad (asynchronous)
GSR to Pad
R
Description
(1)
(1)
IOB Output Switching Characteristics Standard Adjustments, page
(1)
(1)
(1)
www.xilinx.com
T
T
T
T
IOOCECK
IOSRCKO
IOTCECK
IOSRCKT
T
T
Virtex-II Platform FPGAs: DC and Switching Characteristics
IOOCK
IOTCK
T
Symbol
T
T
T
T
T
T
T
T
T
T
IOTLPON
IOTLPHZ
T
IOGSRQ
T
IOCKHZ
IOCKON
T
IOSRHZ
IOSRON
T
IOCKP
IOSRP
IOOLP
IOTHZ
IOOP
IOTP
RPW
GTS
/T
/T
/T
/T
/T
/T
IOCKO
IOCKOCE
IOCKOSR
IOCKT
IOCKTCE
IOCKTSR
0.31/–0.08
0.19/–0.06
0.27/–0.05
0.28/–0.06
0.19/–0.06
0.27/–0.05
1.43
1.72
0.51
1.38
0.80
1.67
4.73
1.76
0.95
1.82
0.61
2.41
1.52
2.39
5.44
-6
Speed Grade
0.34/–0.09
0.21/–0.07
0.30/–0.06
0.31/–0.07
0.21/–0.07
0.30/–0.06
1.51
1.83
0.56
1.45
0.88
1.77
5.20
1.87
1.04
1.94
0.67
2.59
1.67
2.56
5.98
-5
0.39/–0.11
0.24/–0.08
0.34/–0.07
0.35/–0.08
0.24/–0.08
0.34/–0.07
14.
1.74
2.11
0.64
1.67
1.01
2.04
5.98
2.15
1.20
2.22
0.77
2.98
1.92
2.95
6.88
-4
Module 3 of 4
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
13