XC2V500-5FGG456C Xilinx Inc, XC2V500-5FGG456C Datasheet - Page 35

• Manufacturer Part Number: XC2V500-5FGG456C
• Description: FPGA Virtex-II™ Family 500K Gates 6912 Cells 750MHz 0.15um/0.12um (CMOS) Technology 1.5V 456-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V500-5FGG456C

• Package: 456FBGA
• Family Name: Virtex-II™
• Device Logic Units: 6912
• Device System Gates: 500000
• Number Of Registers: 6144
• Maximum Internal Frequency: 750 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 264
• Ram Bits: 589824
• Number Of Labs/clbs: 768
• Total Ram Bits: 589824
• Number Of I /o: 264
• Number Of Gates: 500000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 456-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Clock Multiplexer Buffers
Virtex-II devices have 16 clock input pins that can also be
used as regular user I/Os. Eight clock pads are on the top
edge of the device, in the middle of the array, and eight are
on the bottom edge, as illustrated in
The global clock multiplexer buffer represents the input to
dedicated low-skew clock tree distribution in Virtex-II
devices. Like the clock pads, eight global clock multiplexer
buffers are on the top edge of the device and eight are on
the bottom edge.
Each global clock buffer can either be driven by the clock
pad to distribute a clock directly to the device, or driven by
the Digital Clock Manager (DCM), discussed in
Manager (DCM), page
be driven by local interconnects. The DCM has clock out-
put(s) that can be connected to global clock buffer inputs, as
shown in
DS031-2 (v3.5) November 5, 2007
Product Specification
Figure
R
39.
Multiplier Blocks
29. Each global clock buffer can also
Figure 37: Multipliers (2-column, 4-column, and 6-column)
Figure
38.
Digital Clock
Multiplier Blocks
www.xilinx.com
Virtex-II Platform FPGAs: Functional Description
Multiplier Blocks
Figure 38: Virtex-II Clock Pads
Virtex-II
Device
8 clock pads
8 clock pads
DS031_39_101000
DS031_42_022305
Module 2 of 4
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