XC2VP4-6FG256I Xilinx Inc, XC2VP4-6FG256I Datasheet - Page 60
![no-image](/images/no-image-200.jpg)
XC2VP4-6FG256I
Manufacturer Part Number
XC2VP4-6FG256I
Description
FPGA Virtex-II Pro™ Family 6768 Cells 1200MHz 0.13um/90nm (CMOS) Technology 1.5V 256-Pin FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet
1.XC2VP20-5FGG676C.pdf
(430 pages)
Specifications of XC2VP4-6FG256I
Package
256FBGA
Family Name
Virtex-II ProÂ
Device Logic Units
6768
Number Of Registers
6016
Maximum Internal Frequency
1200 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
140
Ram Bits
516096
Number Of Logic Elements/cells
6768
Number Of Labs/clbs
752
Total Ram Bits
516096
Number Of I /o
140
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2VP4-6FG256I
Manufacturer:
XILINX
Quantity:
200
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DS083 (v4.7) November 5, 2007
Product Specification
Figure 55: Virtex-II Pro Clock Pads
R
Virtex-II Pro
Device
8 clock pads
8 clock pads
Figure 56: Virtex-II Pro Clock Multiplexer Buffer Configuration
DS083-2_42_052902
Clock
Pad
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Clock Distribution
Clock Multiplexer
www.xilinx.com
CLKOUT
CLKIN
DCM
Buffer
Clock
Clock
Pad
O
I
Each global clock multiplexer buffer can be driven either by
the clock pad to distribute a clock directly to the device, or
by the Digital Clock Manager (DCM), discussed in
Clock Manager (DCM), page
plexer buffer can also be driven by local interconnects. The
DCM has clock output(s) that can be connected to global
clock multiplexer buffer inputs, as shown in
Global clock buffers are used to distribute the clock to some
or all synchronous logic elements (such as registers in
CLBs and IOBs, and SelectRAM+ blocks.
Eight global clocks can be used in each quadrant of the
Virtex-II Pro device. Designers should consider the clock
distribution detail of the device prior to pin-locking and floor-
planning. (See the Virtex-II Pro Platform FPGA User
Guide.)
Interconnect
DS083-2_43_122001
Local
51. Each global clock multi-
Figure
Module 2 of 4
56.
Digital
49
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