XC3S1000-4FT256C Xilinx Inc, XC3S1000-4FT256C Datasheet - Page 75

• Manufacturer Part Number: XC3S1000-4FT256C
• Description: FPGA Spartan®-3 Family 1M Gates 17280 Cells 630MHz 90nm Technology 1.2V 256-Pin FTBGA
• Manufacturer: Xilinx Inc

Specifications of XC3S1000-4FT256C

• Package: 256FTBGA
• Family Name: Spartan®-3
• Device Logic Units: 17280
• Device System Gates: 1000000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 173
• Ram Bits: 442368
• Case: BGA
• Dc: 04+

Table 46: Output Timing Adjustments for IOB (Continued)
DS099-3 (v2.5) December 4, 2009
Product Specification
98
LVCMOS33
LVDCI_33
LVDCI_DV2_33
LVTTL
LVCMOS25 with 12mA Drive
Following Signal Standard
Convert Output Time from
and Fast Slew Rate to the
(IOSTANDARD)
R
Slow
Slow
Fast
Fast
12 mA
16 mA
24 mA
12 mA
16 mA
24 mA
12 mA
16 mA
24 mA
12 mA
16 mA
24 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
8 mA
Add the Adjust-
6.38
4.83
4.01
3.92
2.91
2.81
2.49
3.86
1.87
0.62
0.61
0.16
0.14
0.06
0.28
0.26
7.27
4.94
3.98
3.98
2.97
2.84
2.65
4.32
1.87
1.27
1.19
0.42
0.27
0.16
Speed Grade
ment Below
-5
7.34
5.55
4.61
4.51
3.35
3.23
2.86
4.44
2.15
0.71
0.70
0.19
0.16
0.07
0.32
0.30
8.36
5.69
4.58
4.58
3.42
3.26
3.04
4.97
2.15
1.47
1.37
0.48
0.32
0.18
Spartan-3 FPGA Family: DC and Switching Characteristics
-4
Units
www.xilinx.com
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 46: Output Timing Adjustments for IOB (Continued)
Notes:
1.
2.
3.
PCI33_3
SSTL18_I
SSTL18_I_DCI
SSTL18_II
SSTL2_I
SSTL2_I_DCI
SSTL2_II
SSTL2_II_DCI
Differential Standards
LDT_25 (ULVDS_25)
LVDS_25
BLVDS_25
LVDSEXT_25
LVPECL_25
RSDS_25
DIFF_HSTL_II_18
DIFF_HSTL_II_18_DCI
DIFF_SSTL2_II
DIFF_SSTL2_II_DCI
LVCMOS25 with 12mA Drive
Following Signal Standard
Convert Output Time from
and Fast Slew Rate to the
The numbers in this table are tested using the methodology
presented in
conditions set forth in
These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times
that measure when outputs go into a high-impedance state.
For minimums, use the values reported by the Xilinx timing
analyzer.
(IOSTANDARD)
Table 47
Table
and are based on the operating
31,
Table
Add the Adjust-
–0.06
–0.09
–0.15
–0.02
0.74
0.07
0.22
0.30
0.23
0.19
0.13
0.10
0.02
0.16
0.05
0.75
0.13
0.10
Speed Grade
ment Below
-5
34, and
–0.05
–0.07
–0.13
–0.01
0.85
0.07
0.25
0.34
0.26
0.22
0.15
0.11
0.04
0.18
0.06
0.86
0.15
0.11
Table
-4
36.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
75