XC3S100E-4VQG100I Xilinx Inc, XC3S100E-4VQG100I Datasheet - Page 162

FPGA Spartan®-3E Family 100K Gates 2160 Cells 572MHz 90nm (CMOS) Technology 1.2V 100-Pin VTQFP

XC3S100E-4VQG100I

Manufacturer Part Number
XC3S100E-4VQG100I
Description
FPGA Spartan®-3E Family 100K Gates 2160 Cells 572MHz 90nm (CMOS) Technology 1.2V 100-Pin VTQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet

Specifications of XC3S100E-4VQG100I

Package
100VTQFP
Family Name
Spartan®-3E
Device Logic Cells
2160
Device Logic Units
240
Device System Gates
100000
Number Of Registers
1920
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
66
Ram Bits
73728
Number Of Logic Elements/cells
2160
Number Of Labs/clbs
240
Total Ram Bits
73728
Number Of I /o
66
Number Of Gates
100000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
100-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
XC3S100E-4VQG100I
Manufacturer:
XILINX
Quantity:
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Part Number:
XC3S100E-4VQG100I
Manufacturer:
Xilinx Inc
Quantity:
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Part Number:
XC3S100E-4VQG100I
Manufacturer:
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0
DC and Switching Characteristics
162
04/18/08
08/26/09
Date
Version
3.7
3.8
Clarified that Stepping 0 was offered only for -4C and removed Stepping 0 -5 specifications.
Added reference to XAPP459 in
to 3.465V (3.3V + 5%) in
Updated Recommended Operating Conditions for LVCMOS and PCI I/O standards in
Table
footnote recommending use of Timing Analyzer for minimum values. Updated T
T
current speed file and CLB equivalent spec. Added XC3S500E VQG100 to
Replaced T
CLKOUT_PER_JITT_FX in
Updated
Added reference to XAPP459 in
Table
SSTL in
Table 88
Table
PHFD
80. Removed Absolute Minimums from
119, and
107, and updated note 6 for
in
Table
and setup times for T
Figure 78
Table 87
MULCKID
95. Added
Table
to match current speed file. Update T
and
with T
120. Removed V
www.xilinx.com
Table 120
Table
Spread Spectrum
MSCKD
Table
DICK
77. Removed minimum input capacitance from
Table 73
Table 73
for A, B, and P registers in
107. Updated MAX_STEPS equation in
to correct CCLK active edge. Updated links.
Table 107
in
REF
Table
Revision
and
requirements for differential HSTL and differential
note 2. Updated BPI timing in
98. Added note 4 to
paragraph. Revised hold times for T
to add input jitter.
Table
Table
77. Improved recommended max V
86,
Table 92
RPW_IOB
Table
DS312-3 (v3.8) August 26, 2009
Table 106
and
in
102. Updated
Table 88
Table 93
Product Specification
Figure
Table
and note 6 to
Table
to match
and added
Table
78,
PSFD
IOICKPD
109.
96.
78.
and
CCO
in
R

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