XC3S200-4PQ208C Xilinx Inc, XC3S200-4PQ208C Datasheet - Page 121
![no-image](/images/no-image-200.jpg)
XC3S200-4PQ208C
Manufacturer Part Number
XC3S200-4PQ208C
Description
FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 208-Pin PQFP
Manufacturer
Xilinx Inc
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S200-4PQ208C
Package
208PQFP
Family Name
Spartan®-3
Device Logic Units
4320
Device System Gates
200000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
141
Ram Bits
221184
Case
QFP208
Dc
04+
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Table 84: Maximum User I/Os by Package
Electronic versions of the package pinout tables and foot-
prints are available for download from the Xilinx website.
Using a spreadsheet program, the data can be sorted and
reformatted according to any specific needs. Similarly, the
DS099-4 (v2.5) December 4, 2009
Product Specification
Notes:
1.
XC3S1000
XC3S1000
XC3S1500
XC3S1000
XC3S1500
XC3S2000
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S2000
XC3S4000
XC3S5000
XC3S4000
XC3S5000
XC3S200
XC3S200
XC3S400
XC3S200
XC3S400
XC3S200
XC3S400
XC3S400
XC3S400
XC3S50
XC3S50
XC3S50
XC3S50
The CP132, CPG132, FG1156, and FGG1156 packages are being discontinued and are not recommended for new designs. See
http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm
Device
R
FG1156
FG1156
Package
CP132
VQ100
VQ100
PQ208
PQ208
PQ208
TQ144
TQ144
TQ144
FG320
FG320
FG320
FG456
FG456
FG456
FG456
FG676
FG676
FG676
FG676
FG676
FG900
FG900
FG900
FT256
FT256
FT256
(1)
(1)
(1)
Maximum
User I/Os
124
141
141
173
173
173
221
221
221
264
333
333
333
391
487
489
489
489
565
633
633
712
784
63
63
89
97
97
97
Differential
Maximum
www.xilinx.com
Pairs
100
100
100
116
149
149
149
175
221
221
221
221
270
300
300
312
344
29
29
44
46
46
46
56
62
62
76
76
76
ASCII-text file is easily parsed by most scripting programs.
Download the files from the following location:
113
113
113
156
156
156
196
261
261
261
315
403
405
405
405
481
549
549
621
692
http://www.xilinx.com/support/documentation/
data_sheets/s3_pin.zip
I/O
22
22
44
51
51
51
72
83
83
All Possible I/O Pins by Type
Spartan-3 FPGA Family: Pinout Descriptions
DUAL
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
for the latest updates.
DCI
14
14
14
14
14
14
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
VREF
11
12
12
12
16
22
22
24
24
24
29
29
29
32
36
36
36
40
48
48
48
48
48
48
48
55
56
7
7
GCLK
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
N.C.
17
69
98
68
73
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
0
0
0
0
0
1
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