XC3S700AN-4FG484I Xilinx Inc, XC3S700AN-4FG484I Datasheet - Page 25
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XC3S700AN-4FG484I
Manufacturer Part Number
XC3S700AN-4FG484I
Description
FPGA Spartan®-3AN Family 700K Gates 13248 Cells 667MHz 90nm Technology 1.2V 484-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheet
1.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S700AN-4FG484I
Package
484FBGA
Family Name
Spartan®-3AN
Device Logic Units
13248
Device System Gates
700000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
372
Ram Bits
368640
Number Of Logic Elements/cells
13248
Number Of Labs/clbs
1472
Total Ram Bits
368640
Number Of I /o
372
Number Of Gates
700000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-BBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S700AN-4FG484I
Manufacturer:
XILINX
Quantity:
413
Company:
Part Number:
XC3S700AN-4FG484I
Manufacturer:
Xilinx Inc
Quantity:
10 000
I/O Timing
Pin-to-Pin Clock-to-Output Times
Table 21: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
3.
Clock-to-Output Times
T
The numbers in this table are tested using the methodology presented in
Table 10
This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from
DCM output jitter is included in all measurements.
Symbol
ICKOFDCM
T
ICKOF
and
Table
When reading from the Output
Flip-Flop (OFF), the time from the
active transition on the Global
Clock pin to data appearing at the
Output pin. The DCM is in use.
When reading from OFF, the time
from the active transition on the
Global Clock pin to data appearing
at the Output pin. The DCM is not
in use.
13.
Table
Description
26. If the latter is true, add the appropriate Output adjustment from
LVCMOS25
output drive, Fast slew
rate, with DCM
LVCMOS25
output drive, Fast slew
rate, without DCM
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
Conditions
(2)
(2)
, 12 mA
, 12 mA
(3)
Table 30
and are based on the operating conditions set forth in
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
Device
Table
29.
Max
3.18
3.21
2.97
3.39
3.51
4.59
4.88
4.68
4.97
5.06
-5
Speed Grade
Max
3.42
3.27
3.33
3.50
3.99
5.02
5.24
5.12
5.34
5.69
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25