XC3SD3400A-4CSG484C Xilinx Inc, XC3SD3400A-4CSG484C Datasheet - Page 48

• Manufacturer Part Number: XC3SD3400A-4CSG484C
• Description: FPGA Spartan®-3A Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr

Specifications of XC3SD3400A-4CSG484C

• Package: 484LCSBGA
• Family Name: Spartan®-3A
• Device Logic Units: 53712
• Device System Gates: 3400000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 2322432
• Number Of Logic Elements/cells: 53712
• Number Of Labs/clbs: 5968
• Total Ram Bits: 2322432
• Number Of I /o: 309
• Number Of Gates: 3400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1540

Phase Shifter (PS)
Table 40: Recommended Operating Conditions for the PS in Variable Phase Mode
Table 41: Switching Characteristics for the PS in Variable Phase Mode
Notes:
1.
2.
3.
Miscellaneous DCM Timing
Table 42: Miscellaneous DCM Timing
DS610 (v3.0) October 4, 2010
Product Specification
Phase Shifting Range
MAX_STEPS
FINE_SHIFT_RANGE_MIN
FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting
Operating Frequency Ranges
PSCLK_FREQ
(FPSCLK)
Input Pulse Requirements
PSCLK_PULSE
DCM_RST_PW_MIN
The numbers in this table are based on the operating conditions set forth in
The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
The DCM_DELAY_STEP values are provided at the bottom of
Symbol
Symbol
Symbol
(2,3)
Frequency for the PSCLK input
PSCLK pulse width as a percentage of the PSCLK period
Minimum guaranteed delay for variable phase shifting
Maximum allowed number of
DCM_DELAY_STEP steps for a given
CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE, double
the effective clock period.
Minimum duration of a RST pulse width
Description
Description
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
Description
Table
37.
CLKIN < 60 MHz
CLKIN ≥ 60 MHz
Table 7
and
Table
40%
Min
1
±[INTEGER(10 • (T
±[INTEGER(15 • (T
40.
DCM_DELAY_STEP_MAX]
DCM_DELAY_STEP_MIN]
-5
Phase Shift Amount
60%
Speed Grade
Max
167
±[MAX_STEPS •
±[MAX_STEPS •
Min
3
40%
Min
1
CLKIN
CLKIN
Max
-4
–
– 3 ns))]
– 3 ns))]
Max
60%
167
CLKIN
cycles
Units
Units
MHz
Units
steps
–
ns
ns
48