XC5VLX110-1FFG676I Xilinx Inc, XC5VLX110-1FFG676I Datasheet - Page 382
XC5VLX110-1FFG676I
Manufacturer Part Number
XC5VLX110-1FFG676I
Description
FPGA Virtex®-5 Family 110592 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110-1FFG676I
Package
676FCBGA
Family Name
Virtex®-5
Device Logic Units
110592
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
440
Ram Bits
4718592
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
4718592
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110-1FFG676I
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 8: Advanced SelectIO Logic Resources
382
OSERDES VHDL and Verilog Instantiation Templates
Clock Event 2
The reset pulse is deasserted on the rising edge of CLKDIV. The difference in propagation
delay between the two OSERDES causes the SR input to come out of reset on two different
CLK cycles. Without internal retiming, OSERDES1 finishes reset one CLK cycle before
OSERDES0 and both OSERDES are asynchronous.
Clock Event 3
The release of the reset signal at the SR input is retimed internally to CLKDIV. This
synchronizes OSERDES0 and OSERDES1.
Clock Event 4
The release of the reset signal at the SR input is retimed internally to CLK.
The Libraries Guide includes instantiation templates of the OSERDES module in VHDL
and Verilog.
www.xilinx.com
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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