XC5VLX110T-2FF1136I Xilinx Inc, XC5VLX110T-2FF1136I Datasheet - Page 17

• Manufacturer Part Number: XC5VLX110T-2FF1136I
• Description: FPGA Virtex®-5 Family 110592 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX110T-2FF1136I

• Package: 1136FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 110592
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 640
• Ram Bits: 5455872
• Number Of Logic Elements/cells: 110592
• Number Of Labs/clbs: 8640
• Total Ram Bits: 5455872
• Number Of I /o: 640
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1136-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 33: GTP_DUAL Tile User Clock Switching Characteristics
Table 34: GTP_DUAL Tile Transmitter Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
Notes:
1.
2.
3.
Symbol
F
F
TXOUT
RXREC
T
T
T
T
Clocking must be implemented as described in UG196: Virtex-5 FPGA RocketIO GTP Transceiver User Guide
Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP_DUAL sites.
Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1.
All jitter values are based on a Bit-Error Ratio of 1e
RX2
TX2
RX
TX
T
V
TXOOBTRANS
TXOOBVDPP
T
Symbol
F
D
D
D
LLSKEW
T
T
T
D
D
T
T
T
T
T
D
T
D
T
D
GTPTX
J3.75
J1.25
J1.00
J3.75
J1.25
J1.00
J500
J500
J100
J100
RTX
FTX
J3.2
J2.5
J2.0
J3.2
J2.5
J2.0
TXOUTCLK maximum frequency
RXRECCLK maximum frequency
RXUSRCLK maximum frequency
RXUSRCLK2 maximum frequency
TXUSRCLK maximum frequency
TXUSRCLK2 maximum frequency
Description
Serial data rate range
TX Rise time
TX Fall time
TX lane-to-lane skew
Electrical idle amplitude
Electrical idle transition time
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
Total Jitter
Deterministic Jitter
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
Description
–12
RXDATAWIDTH = 0
RXDATAWIDTH = 1
TXDATAWIDTH = 0
TXDATAWIDTH = 1
.
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Conditions
3.75 Gb/s
3.20 Gb/s
2.50 Gb/s
2.00 Gb/s
1.25 Gb/s
1.00 Gb/s
500 Mb/s
100 Mb/s
(1)
187.5
187.5
Min
375
375
375
350
375
350
0.1
-3
Speed Grade
187.5
187.5
Typ
375
350
375
140
120
375
375
350
-2
F
GTPMAX
Max
0.35
0.19
0.35
0.19
0.30
0.14
0.30
0.14
0.20
0.10
0.20
0.10
0.10
0.04
0.02
0.01
320
320
320
320
160
320
320
160
855
20
40
-1
Units
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Gb/s
mV
ps
ps
ps
ns
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
17