XC5VLX30T-2FF323I Xilinx Inc, XC5VLX30T-2FF323I Datasheet - Page 61
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XC5VLX30T-2FF323I
Manufacturer Part Number
XC5VLX30T-2FF323I
Description
FPGA Virtex®-5 Family 30720 Cells 65nm (CMOS) Technology 1V 323-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Specifications of XC5VLX30T-2FF323I
Package
323FCBGA
Family Name
Virtex®-5
Device Logic Units
30720
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
172
Ram Bits
1327104
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1327104
Number Of I /o
172
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
323-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX30T-2FF323I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Table 81: Miscellaneous Timing Parameters
Table 82: Frequency Synthesis
Table 83: DCM Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
Time Required to Achieve LOCK
T
T
T
T
T
T
T
T
T
T
T
Fine Phase Shifting
T
T
Delay Lines
T
T
T
T
CLKFX_MULTIPLY
CLKFX_DIVIDE
T
T
T
DLL_240
DLL_120_240
DLL_60_120
DLL_50_60
DLL_40_50
DLL_30_40
DLL_24_30
DLL_30
FX_MIN
FX_MAX
DLL_FINE_SHIFT
RANGE_MS
RANGE_MR
TAP_MS_MIN
TAP_MS_MAX
TAP_MR_MIN
TAP_MR_MAX
DMCCK_PSEN
DMCCK_PSINCDEC
DMCKO_PSDONE
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
Symbol
/ T
DMCKC_PSEN
/ T
Symbol
DMCKC_PSINCDEC
Attribute
DLL output – Frequency range > 240 MHz
DLL output – Frequency range 120 - 240 MHz
DLL output – Frequency range 60 - 120 MHz
DLL output – Frequency range 50 - 60 MHz
DLL output – Frequency range 40 - 50 MHz
DLL output – Frequency range 30 - 40 MHz
DLL output – Frequency range 24 - 30 MHz
DLL output – Frequency range < 30 MHz
DFS outputs
Multiplication factor for DLL lock time with Fine Shift
Absolute shifting range in maximum speed mode
Absolute shifting range in maximum range mode
Tap delay resolution (Min) in maximum speed mode
Tap delay resolution (Max) in maximum speed mode
Tap delay resolution (Min) in maximum range mode
Tap delay resolution (Max) in maximum range mode
(2)
PSEN Setup/Hold
PSINCDEC Setup/Hold
Clock to out of PSDONE
Description
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Description
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Min
2
1
1300.00
2000.00
3600.00
5000.00
5000.00
1.20
0.00
1.20
0.00
1.00
250.00
900.00
80.00
10.00
10.00
10.00
30.00
10.00
40.00
-3
2.00
7.00
7.00
-3
Speed Grade
Speed Grade
1300.00
2000.00
3600.00
5000.00
5000.00
250.00
900.00
1.35
0.00
1.35
0.00
1.12
30.00
40.00
80.00
10.00
10.00
10.00
10.00
2.00
7.00
7.00
-2
-2
Max
1300.00
2000.00
3600.00
5000.00
5000.00
33
32
250.00
900.00
80.00
10.00
10.00
10.00
30.00
10.00
40.00
1.56
0.00
1.56
0.00
1.30
2.00
7.00
7.00
-1
-1
Units
Units
ms
ms
ns
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ps
ps
ps
ps
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