XC5VLX85-2FF676I Xilinx Inc, XC5VLX85-2FF676I Datasheet - Page 116

• Manufacturer Part Number: XC5VLX85-2FF676I
• Description: FPGA Virtex®-5 Family 82944 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX85-2FF676I

• Package: 676FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 82944
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 440
• Ram Bits: 3538944
• Number Of Logic Elements/cells: 82944
• Number Of Labs/clbs: 6480
• Total Ram Bits: 3538944
• Number Of I /o: 440
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chapter 4: Block RAM
116
X-Ref Target - Figure 4-1
Table 4-2: True Dual-Port Names and Descriptions
DI[A|B]
DIP[A|B]
ADDR[A|B]
WE[A|B]
EN[A|B]
SSR[A|B]
CLK[A|B]
DO[A|B]
DOP[A|B]
REGCE[A|B]
CASCADEINLAT[A|B]
Port Name
(1)
(1)
CASCADEOUTREGA
Figure 4-1: True Dual-Port Data Flows
CASCADEOUTLATA
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CASCADEINREGA
CASCADEINLATA
DIA
DIPA
ADDRA
WEA
ENA
SSRA
REGCEA
DIB
DIPB
ADDRB
WEB
ENB
SSRB
REGCEB
Data Input Bus
Data Input Parity Bus, can be used for additional data inputs
Address Bus
Byte-wide Write Enable
When inactive no data is written to the block RAM and the
output bus remains in its previous state
Synchronous Set/Reset for either latch or register modes
Clock Input
Data Output Bus
Data Output Parity Bus, can be used for additional data
outputs
Output Register Enable
Cascade input pin for 64K x 1 mode when optional output
registers are not enabled
CLKA
CLKB
36-Kbit Block RAM
Memory
Port A
Port B
36 Kb
Array
CASCADEOUTLATB
CASCADEOUTREGB
CASCADEINLATB
CASCADEINREGB
DOPB
DOPA
DOB
DOA
Description
ug0190_4_01_032106
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010