XC6VCX240T-2FFG784C Xilinx Inc, XC6VCX240T-2FFG784C Datasheet - Page 34

• Manufacturer Part Number: XC6VCX240T-2FFG784C
• Description: FPGA Virtex®-6 CXT Family 241152 Cells 40nm (CMOS) Technology 1V 784-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 CXTr

Specifications of XC6VCX240T-2FFG784C

• Package: 784FCBGA
• Family Name: Virtex®-6 CXT
• Device Logic Units: 241152
• Number Of Registers: 301440
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 400
• Ram Bits: 15335424
• Number Of Logic Elements/cells: 241152
• Number Of Labs/clbs: 18840
• Total Ram Bits: 15335424
• Number Of I /o: 400
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 784-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Input/Output Delay Switching Characteristics
Table 46: Input/Output Delay Switching Characteristics
CLB Switching Characteristics
Table 47: CLB Switching Characteristics
DS153 (v1.6) February 11, 2011
Product Specification
Notes:
1.
2.
3.
4.
IDELAYCTRL
T
F
IDELAYCTRL_REF_PRECISION REFCLK precision
T
IODELAY
T
T
T
T
T
T
T
T
T
Combinatorial Delays
T
T
T
T
T
T
AXA
AXB
AXC
AXD
DLYCCO_RDY
IDELAYCTRL_REF
IDELAYCTRL_RPW
IDELAYRESOLUTION
IDELAYPAT_JIT
IODELAY_CLK_MAX
IODCCK_CE
IODCK_INC
IODCCK_RST
IODDO_T
IODDO_IDATAIN
IODDO_ODATAIN
ILO
ITO
When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
When HIGH_PERFORMANCE mode is set to TRUE
When HIGH_PERFORMANCE mode is set to FALSE.
Delay depends on IODELAY tap setting. See the TRACE report for actual values.
Symbol
/ T
Symbol
/ T
/ T
IODCKC_INC
IODCKC_CE
IODCKC_RST
An – Dn LUT address to A
An – Dn LUT address to AMUX/CMUX
An – Dn LUT address to BMUX_A
An – Dn inputs to A – D Q outputs
AX inputs to AMUX output
AX inputs to BMUX output
AX inputs to CMUX output
AX inputs to DMUX output
Reset to Ready for IDELAYCTRL
REFCLK frequency
Minimum Reset pulse width
IODELAY Chain Delay Resolution
Pattern dependent period jitter in delay chain for clock
pattern.
Pattern dependent period jitter in delay chain for
random data pattern.
Pattern dependent period jitter in delay chain for
random data pattern.
Maximum frequency of CLK input to IODELAY
CE pin Setup/Hold with respect to CK
INC pin Setup/Hold with respect to CK
RST pin Setup/Hold with respect to CK
TSCONTROL delay to MUXE/MUXF switching and
through IODELAY
Propagation delay through IODELAY
Propagation delay through IODELAY
(1)
Description
Description
(2)
(3)
www.xilinx.com
0.31/–0.00
0.69/–0.08
0.65/–0.09
Note 4
Note 4
Note 4
0.08
0.23
0.37
0.79
0.42
0.47
0.52
0.55
±10
200
300
-2
50
±5
±9
-2
3
0
Virtex-6 CXT Family Data Sheet
1/(32 x 2 x F
Speed Grade
Speed Grade
0.69/–0.08
0.65/–0.09
0.31/–0.00
REF
Note 4
Note 4
0.08
0.41
0.91
0.48
0.53
0.60
0.63
Note 4
0.25
-1
200
±10
300
50
±5
±9
-1
3
)
0
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
per tap
per tap
per tap
Units
Units
MHz
MHz
MHz
µs
ns
ps
ps
ps
ps
ns
ns
ns
ps
ps
ps
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