XC6VLX75T-1FFG784C Xilinx Inc, XC6VLX75T-1FFG784C Datasheet - Page 2
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XC6VLX75T-1FFG784C
Manufacturer Part Number
XC6VLX75T-1FFG784C
Description
FPGA Virtex®-6 Family 74496 Cells 40nm (CMOS) Technology 1V 784-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™ 6 LXTr
Datasheet
1.XC6VHX250T-1FFG1154C.pdf
(11 pages)
Specifications of XC6VLX75T-1FFG784C
Package
784FCBGA
Family Name
Virtex®-6
Device Logic Units
74496
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
360
Ram Bits
5750784
Number Of Logic Elements/cells
74496
Number Of Labs/clbs
5820
Total Ram Bits
5750784
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
784-BBGA, FCBGA
No. Of Logic Blocks
11640
No. Of Macrocells
74496
Family Type
Virtex-6
No. Of Speed Grades
1
No. Of I/o's
360
Clock Management
PLL
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC6VLX75T-1FFG784C
Manufacturer:
XILINX
Quantity:
287
Company:
Part Number:
XC6VLX75T-1FFG784C
Manufacturer:
XILINX
Quantity:
120
Company:
Part Number:
XC6VLX75T-1FFG784C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Virtex-6 FPGA Feature Summary
Table 1: Virtex-6 FPGA Feature Summary by Device
DS150 (v2.2) January 28, 2010
Advance Product Specification
Notes:
1.
2.
3.
4.
5.
6.
7.
XC6VLX75T
XC6VLX130T 128,000
XC6VLX195T 199,680
XC6VLX240T 241,152
XC6VLX365T 364,032
XC6VLX550T 549,888
XC6VLX760
XC6VSX315T 314,880
XC6VSX475T 476,160
XC6VHX250T 251,904
XC6VHX255T 253,440
XC6VHX380T 382,464
XC6VHX565T 566,784
Device
Each Virtex-6 FPGA slice contains four LUTs and eight flip-flops, only some slices can use their LUTs as distributed RAM or SRLs.
Each DSP48E1 slice contains a 25 x 18 multiplier, an adder, and an accumulator.
Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18 Kb blocks.
Each CMT contains two mixed-mode clock managers (MMCM).
This table lists individual Ethernet MACs per device.
Does not include configuration Bank 0.
This number does not include GTX or GTH transceivers.
758,784 118,560
74,496
Logic
Cells
Slices
11,640
20,000
31,200
37,680
56,880
85,920
49,200
74,400
39,360
39,600
59,760
88,560
Configurable Logic
Blocks (CLBs)
(1)
Distributed
RAM (Kb)
1,045
1,740
3,040
3,650
4,130
6,200
8,280
5,090
7,640
3,040
3,050
4,570
6,370
Max
DSP48E1
Slices
1,344
2,016
288
480
640
768
576
864
864
576
576
864
864
(2)
18 Kb
1,264
1,440
1,408
2,128 1,064 38,304
1,008
1,032
1,536
1,824
312
528
688
832
832
Block RAM Blocks
(3)
www.xilinx.com
36 Kb
156
264
344
416
416
632
720
704
504
516
768
912
12,384
14,976
14,976
22,752
25,920
25,344
18,144
18,576
27,648
32,832
5,616
9,504
Max
(Kb)
MMCMs
10
10
12
12
18
18
12
18
12
12
18
18
6
(4)
PCI Express
Blocks for
Interface
1
2
2
2
2
2
0
2
2
4
2
4
4
Ethernet
MACs
4
4
4
4
4
4
0
4
4
4
2
4
4
(5)
Virtex-6 Family Overview
GTX
Transceivers
12
20
20
24
24
36
24
36
48
24
48
48
0
Maximum
GTH
24
24
24
0
0
0
0
0
0
0
0
0
0
Banks
Total
I/O
15
15
18
18
30
30
18
21
12
18
18
9
8
(6)
1200
1200
User
I/O
Max
360
600
600
720
720
720
840
320
480
720
720
(7)
2