LFE2M50E-7FN672C LATTICE SEMICONDUCTOR, LFE2M50E-7FN672C Datasheet - Page 240
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LFE2M50E-7FN672C
Manufacturer Part Number
LFE2M50E-7FN672C
Description
FPGA LatticeECP2M Family 48000 Cells 90nm (CMOS) Technology 1.2V 672-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M50E-7FN672C
Package
672FBGA
Family Name
LatticeECP2M
Device Logic Units
48000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
372
Ram Bits
4246528
In System Programmability
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M50E-7FN672C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LFE2M50E-7FN672C
Manufacturer:
LATTICE
Quantity:
20 000
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Lattice Semiconductor
LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA
Number
VCCIO
GNDIO
VCCIO
GNDIO
VCCIO
GNDIO
VCCIO
VCCIO
GNDIO
VCCIO
GNDIO
VCCIO
GNDIO
Ball
M12
M13
N14
N15
N16
M16
H16
H13
H12
G16
H15
G15
G14
G13
H11
L12
L13
L16
K16
L14
L15
K13
K14
K11
K15
E16
F15
F16
F14
F13
J16
J15
J14
J13
J11
J12
RLM0_PLLCAP
Function
Ball/Pad
GNDIO8
GNDIO3
GNDIO3
GNDIO3
GNDIO2
GNDIO2
VCCIO8
VCCIO8
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO2
PR53B
PR53A
PR52B
PR52A
PR51B
PR51A
PR50B
PR50A
PR49B
PR49A
PR48B
PR48A
PR47B
PR47A
PR45B
PR45A
PR44B
PR44A
PR43B
PR43A
PR42B
PR42A
PR32B
PR32A
PR31B
PR31A
PR28B
PR28A
PR27B
PR27A
PR25B
PR25A
PR24B
PR24A
PR14B
LFE2M20E/SE
Bank
8
8
8
8
8
8
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
8
8
8
8
8
8
8
8
8
8
3
3
3
3
3
3
3
3
2
2
2
-
-
-
-
-
-
DOUT/CSON/CSSPI1N
RLM0_GDLLC_FB_A
RLM0_GPLLC_FB_A
RLM0_GDLLT_FB_A
RLM1_SPLLC_FB_A
RLM0_GDLLC_IN_A
RLM0_GPLLC_IN_A
RLM0_GPLLT_FB_A
RLM1_SPLLT_FB_A
RLM0_GDLLT_IN_A
RLM0_GPLLT_IN_A
RLM1_SPLLC_IN_A
RLM1_SPLLT_IN_A
PCLKC2_0/RDQ22
PCLKT2_0/RDQ22
Dual Function
D0/SPIFASTN
D7/SPID0***
DI/CSSPI0N
BUSY/SISPI
PCLKC3_0
PCLKT3_0
VREF2_3
VREF1_3
WRITEN
RDQ22
RDQ22
CS1N
CSN
D1
D2
D3
D4
D5
D6
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
C
C
C
C
C
C
T
T
C
T
C
T
C
T
C
T
C
T
C
T
T
T
C
T
T
4-137
RLM0_PLLCAP
Function
Ball/Pad
GNDIO8
GNDIO3
GNDIO3
GNDIO3
GNDIO2
GNDIO2
VCCIO8
VCCIO8
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO2
PR68B
PR68A
PR67B
PR67A
PR66B
PR66A
PR65B
PR65A
PR64B
PR64A
PR63B
PR63A
PR62B
PR62A
PR60B
PR60A
PR59B
PR59A
PR58B
PR58A
PR57B
PR57A
PR42B
PR42A
PR41B
PR41A
PR38B
PR38A
PR37B
PR37A
PR35B
PR35A
PR34B
PR34A
PR14B
LatticeECP2/M Family Data Sheet
Bank
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
-
-
-
-
-
-
RLM0_GPLLT_FB_A/RDQS57***
LFE2M35E/SE
RLM0_GDLLC_IN_A**/RDQ57
RLM0_GPLLC_IN_A**/RDQ57
RLM0_GDLLT_IN_A**/RDQ57
RLM0_GPLLT_IN_A**/RDQ57
RLM0_GDLLC_FB_A/RDQ57
RLM0_GPLLC_FB_A/RDQ57
RLM0_GDLLT_FB_A/RDQ57
DOUT/CSON/CSSPI1N
RLM2_SPLLC_FB_A
RLM2_SPLLT_FB_A
RLM2_SPLLC_IN_A
RLM2_SPLLT_IN_A
PCLKC2_0/RDQ32
PCLKT2_0/RDQ32
D0/SPIFASTN
D7/SPID0***
DI/CSSPI0N
BUSY/SISPI
PCLKC3_0
PCLKT3_0
VREF2_3
VREF1_3
Function
WRITEN
RDQ32
RDQ32
RDQ15
CS1N
Dual
CSN
Pinout Information
D1
D2
D3
D4
D5
D6
Differential
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C(LVDS)*
C(LVDS)*
C(LVDS)*
C(LVDS)*
C(LVDS)*
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
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