LFE2M50SE-6FN672I LATTICE SEMICONDUCTOR, LFE2M50SE-6FN672I Datasheet - Page 37
LFE2M50SE-6FN672I
Manufacturer Part Number
LFE2M50SE-6FN672I
Description
FPGA LatticeECP2M Family 48000 Cells 90nm (CMOS) Technology 1.2V 672-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M50SE-6FN672I
Package
672FBGA
Family Name
LatticeECP2M
Device Logic Units
48000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
372
Ram Bits
4246528
In System Programmability
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M50SE-6FN672I
Manufacturer:
LATTICE
Quantity:
6
Company:
Part Number:
LFE2M50SE-6FN672I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 2-31. Output and Tristate Block for Left, Right and Bottom Edges
DQSXFER
DQSXFER
ONEG1
ONEG0
ONEG1
ONEG0
OPOS1
OPOS0
OPOS1
OPOS0
(CLKA)
(CLKB)
ECLK1
ECLK2
ECLK1
ECLK2
CLKA
CLKB
CLK1
CLK1
TD
TD
* Shared with input register
Clock Transfer
Clock Transfer
Registers
Registers
D
D
D-Type*
D-Type*
D-Type
D-Type
D
D
Tristate Logic
Tristate Logic
Q
Q
Q
Q
*
*
D
D
Latch
Latch
Q
Q
0
1
0
1
0
1
0
1
2-34
Note: Simplified version does not show CE and SET/RESET details
0
1
0
1
0
1
0
1
D
D
D
D
D
D
D
D
/LATCH
/LATCH
/LATCH
/LATCH
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
D-Type
LatticeECP2/M Family Data Sheet
Q
Q
Q
Q
Q
Q
Q
Q
Comp PIO (B) in LVDS I/O Pair
True PIO (A) in LVDS I/O Pair
D
D
D
D
DDR Output
DDR Output
Latch
Latch
Latch
Latch
Registers
Registers
Q
Q
Q
Q
Output Logic
Output Logic
0
1
0
1
0
1
0
1
0
1
0
1
Programmable
Programmable
Control
Control
0
1
0
1
Architecture
0
1
0
1
DO
DO
TO
TO
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