LFEC1E-4TN144C LATTICE SEMICONDUCTOR, LFEC1E-4TN144C Datasheet - Page 13
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LFEC1E-4TN144C
Manufacturer Part Number
LFEC1E-4TN144C
Description
FPGA LatticeEC Family 1500 Cells 378MHz 130nm (CMOS) Technology 1.2V 144-Pin TQFP
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC1E-4TN144C
Package
144TQFP
Family Name
LatticeEC
Device Logic Units
1500
Maximum Internal Frequency
378 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
97
Ram Bits
18432
In System Programmability
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC1E-4TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
grammed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after
adjustment and not relock until the t
allows the user to adjust the phase and duty cycle of the CLKOS output.
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated
with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. The input clock divider
is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The post
scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the fre-
quency range. The secondary divider is used to derive lower frequency outputs.
Figure 2-11. PLL Diagram
Figure 2-12 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block.
Figure 2-12. PLL Primitive
CLKFB
(PLL internal),
from clock net
(CLKOP) or
from a user
clock (PIN or logic)
from CLKOP
(from routing or
external pin)
CLKI
RST
CLKFB
CLKI
Input Clock
Divider
(CLKI)
EPLLB
Feedback
(CLKFB)
Divider
LOCK
Dynamic Delay Adjustment
CLKOP
LOCK
parameter has been satisfied. Additionally, the phase and duty cycle block
Adjust
Delay
DDAIDEL[2:0]
DDA MODE
Controlled
Oscillator
DDAILAG
2-10
Voltage
DDAIZR
VCO
CLKFB
CLKI
RST
Post Scalar
(CLKOP)
Divider
EHXPLLB
LatticeECP/EC Family Data Sheet
Phase/Duty
Secondary
(CLKOK)
Divider
CLKOP
CLKOS
CLKOK
LOCK
DDAOZR
DDAOLAG
DDAODEL[2:0]
Select
Clock
Architecture
LOCK
CLKOS
CLKOP
CLKOK
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