AD421BN Analog Devices Inc, AD421BN Datasheet - Page 3

• Manufacturer Part Number: AD421BN
• Description: DAC 1-CH Delta-Sigma 16-Bit 16-Pin PDIP
• Manufacturer: Analog Devices Inc

Specifications of AD421BN

• Package: 16PDIP
• Resolution: 16 Bit
• Conversion Rate: 125 SPS
• Architecture: Delta-Sigma
• Digital Interface Type: Serial (3-Wire)
• Number Of Outputs Per Chip: 1
• Output Type: Current
• Full Scale Error: ±0.2 %FSR
• Integral Nonlinearity Error: ±0.01 %FSR
• Maximum Settling Time: 8000(Typ) us
• Rohs Status: RoHS non-compliant
• Settling Time: 8µs
• Number Of Bits: 16
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1.95mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)

REV. C
TIMING CHARACTERISTICS
Parameter
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
Specifications subject to change without notice.
Guaranteed by characterization at initial product release, not production tested.
See Figures 1 and 2.
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
CK
CL
CH
DW
DS
DH
LD
LL
LH
input.
CLOCK
LATCH
DATA
CLOCK
LATCH
DATA
Figure 1. Serial Interface Waveforms (Normal Data Load)
(B Versions)
100
50
50
30
30
0
50
50
50
1, 2, 3
1
0
Figure 2. Serial Interface Timing Diagram
1 1
(V
CC
= +3 V to +5 V, T
0 0
CC
) and timed from a voltage level of (V
1
WORD "N"
t
0
C L
t
D S
–3–
0
t
A
D W
1
t
= T
C K
1
MIN
t
1
D H
to T
t
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
C H
0
t
MAX
L D
0
t
LL
unless otherwise noted)
1 1
IN
+ V
IL
)/2; tr and tf should not exceed 1 µs on any digital
t
1
WORD "N +1"
L H
0
0
1
Conditions/Comments
Data Clock Period
Data Clock Low Time
Data Clock High Time
Data Stable Width
Data Setup Time
Data Hold Time
Latch Delay Time
Latch Low Time
Latch High Time
AD421