RT8202AGQW Richtek USA Inc, RT8202AGQW Datasheet - Page 12

• Manufacturer Part Number: RT8202AGQW
• Description: IC PWM CTRLR SYNC BUCK 16WQFN
• Manufacturer: Richtek USA Inc

Specifications of RT8202AGQW

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Voltage - Supply: 4.5 V ~ 5.5 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Duty Cycle: -

RT8202/A/B
traces, making a Kelvin sense connection to the sense
resistor.
MOSFET Gate Driver (UGATE, LGATE)
The high side driver is designed to drive high current, low
R
driver, 5V bias voltage is delivered from VDDP supply. The
average drive current is proportional to the gate charge at
V
drive current is supplied by the flying capacitor between
BOOT and PHASE pins.
A dead time to prevent shoot through is internally
generated between high side MOSFET off to low side
MOSFET on, and low side MOSFET off to high side
MOSFET on.
The low side driver is designed to drive high current, low
R
that drives LGATE low is robust, with a 0.6Ω typical on-
resistance. A 5V bias voltage is delivered form VDDP
supply. The instantaneous drive current is supplied by the
flying capacitor between VDDP and PGND.
For high current applications, some combinations of high
and low side MOSFETs might be encountered that will
cause excessive gate-drain coupling, which can lead to
efficiency killing, EMI producing shoot through currents.
This is often remedied by adding a resistor in series with
BOOT, which increases the turn-on time of the high side
MOSFET without degrading the turn-off time (Figure 4).
Power Good Output (PGOOD)
The power good output is an open-drain output and requires
a pull up resistor. When the output voltage is 15% above
or 10% below its set voltage, PGOOD gets pulled low. It
is held low until the output voltage returns to within these
tolerances once more. In soft start, PGOOD is actively
www.richtek.com
12
GS
DS(ON)
DS(ON)
= 5V times switching frequency. The instantaneous
Figure 4. Reducing the UGATE Rise Time
N-MOSFET(s). The internal pull-down transistor
N-MOSFET(s). When configured as a floating
UGATE
PHASE
BOOT
R
+5V
V
IN
held low and is allowed to transition high until soft start is
over and the output reaches 93% of its set voltage. There
is a 2.5μs delay built into PGOOD circuitry to prevent
false transition.
POR, UVLO and Soft-Start
Power on reset (POR) occurs when VDD rises above to
approximately 4.3V, the RT8202/A/B will reset the fault
latch and preparing the PWM for operation. Below
4.1V
inhibits switching by keeping UGATE and LGATE low.
A built-in soft-start is used to prevent surge current from
power supply input after EN/DEM is enabled. It clamps
the ramping of internal reference voltage which is compared
with FB signal. The typical soft-start duration is 1.35ms.
Furthermore, the maximum allowed current limit is
segment in 2 steps during 1.35ms period.
Output Over Voltage Protection (OVP)
The output voltage can be continuously monitored for over
voltage protection. When the output voltage exceeds 15%
of the its set voltage threshold, over voltage protection is
triggered and the low side MOSFET is latched on. This
activates the low side MOSFET to discharge the output
capacitor.
RT8202/A/B is latched once OVP is triggered and can
only be released by VDD or EN/DEM power on reset. There
is 20us delay built into the over voltage protection circuit
to prevent false transitions.
Output Under Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage protection. When the output voltage is less than
70% of its set voltage threshold, under voltage protection
is triggered and then both UGATE and LGATE gate drivers
are forced low. In order to remove the residual charge on
the output capacitor during the under voltage period, if
PHASE is greater than 1V, the LGATE is forced high until
PHASE is lower than 1V. There is 2.5us delay built into
the under voltage protection circuit to prevent false
transitions. During soft-start, the UVP will be blanked
around 3.1ms.
(MIN)
, the VDD under voltage-lockout (UVLO) circuitry
DS8202/A/B-04 March 2011