4304-52 Peregrine Semiconductor, 4304-52 Datasheet - Page 3

• Manufacturer Part Number: 4304-52
• Description: IC DSA 6BIT 75 OHM 20-QFN
• Manufacturer: Peregrine Semiconductor
• Series: UltraCMOS™r

Specifications of 4304-52

• Attenuation Value: 31.5dB
• Tolerance: ±0.15dB
• Frequency Range: 0 ~ 2GHz
• Impedance: 75 Ohm
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1046-1031-2

PE4304
Product Specification
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE4304 Digital Step Attenuator.
J9 is used in conjunction with the supplied DC cable
to supply V
negative voltage generator is desired, then do not
connect –V
V
J1 should be connected to the parallel port of a PC
with the supplied ribbon cable. The evaluation
software is written to operate the DSA in serial
mode, so Switch 7 (P/S) should be ON with all other
switches off. Using the software, enable or disable
each attenuation setting to the desired combined
attenuation. The software automatically programs
the DSA each time an attenuation state is enabled or
disabled.
To evaluate the Power up options, first disconnect
the parallel ribbon cable from the evaluation board.
The parallel cable must be removed to prevent the
PC parallel port from biasing the control pins to
unknown states. During power up in serial mode (P/
S=1 and LE=0) or in parallel mode with P/S=0 and
LE=1, the default power-up signal attenuation is set
to the value present on the six control bits on the six
parallel data inputs (C0.5 to C16). This allows any
one of the 64 attenuation settings to be specified as
the power-up state.
To power up in Parallel mode (P/S=0) with LE=0, the
control bits are automatically set to one of four
possible values. These four values are selected by
the two power-up control bits, PUP1 and PUP2, as
shown in the Parallel PUP Truth Table (Table 6).
Document No. 70-0066-04 │ www.psemi.com
DD
is desired, then apply -3V.
DD
DD
, GND, and –V
(Black banana plug). If an external –
Note: Resistors on pins 1 and 3
are required to avoid package
resonance and meet error
specifications over frequency.
DD
. If use of the internal
Figure 4. Evaluation Board Layout
Peregrine Specification 101/0112
Figure 5. Evaluation Board Schematic
Peregrine Specification 102/0142
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
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