PE43502MLI-Z Peregrine Semiconductor, PE43502MLI-Z Datasheet - Page 7

• Manufacturer Part Number: PE43502MLI-Z
• Description: IC RF DSA 5-BIT 50 OHM 24-QFN
• Manufacturer: Peregrine Semiconductor
• Series: UltraCMOS™, HaRP™r

Specifications of PE43502MLI-Z

• Attenuation Value: 15.5dB
• Tolerance: ±0.3dB
• Frequency Range: 9kHz ~ 6GHz
• Impedance: 50 Ohm
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1046-1045-2

PE43502
Product Specification
Figure 15. Serial Timing Diagram
Figure 16. Latched-Parallel/Direct-Parallel Timing Diagram
Table 10. Serial Interface AC Characteristics
V
Document No. 70-0247-06 │ www.psemi.com
Symbol Parameter
DO[6:0]
DO[5:1]
DD
DI[5:1]
T
T
T
T
T
T
T
DI[5:1]
T
T
F
T
T
T
T
CLKH
LEPW
PSSU
CLK
CLKL
LESU
DISU
SISU
CLK
ASU
PSH
SIH
DIH
P/S
= 3.3 or 5.0 V, -40° C < T
AH
PD
LE
SI
P/S
LE
Serial clock frequency
Serial clock HIGH time
Serial clock LOW time
Last serial clock rising edge
setup time to Latch Enable
rising edge
Latch Enable minimum pulse
width
Serial data setup time
Serial data hold time
Parallel data setup time
Parallel data hold time
Address setup time
Address hold time
Parallel/Serial setup time
Parallel/Serial hold time
Digital register delay (internal)
T
SISU
T
PSSU
T
T
DISU
SIH
T
D[0]
PSSU
T
DIPD
VALID
T
D[1]
T
DISU
CLKL
T
A
LEPW
< 85° C, unless otherwise specified
Bits can either be set to logic high or logic low
D[0], D[6] and D[7] must be set to logic low
D[2]
VALID
T
PD
T
Min.
100
100
100
100
100
100
PSIH
30
30
10
30
10
10
-
-
T
DIH
D[3]
Max.
10
10
-
-
-
-
-
-
-
-
-
-
-
-
D[4]
Unit
T
MHz
CLKH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D[5]
D[6]
Table 11. Parallel and Direct Interface AC
V
DD
Symbol
D[7]
= 3.3 or 5.0 V, -40° C < T
T
T
T
T
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
T
T
T
LEPW
PSSU
DISU
DIPD
PSIH
DIH
PD
T
LESU
T
LEPW
Characteristics
T
T
Latch Enable minimum
pulse width
Parallel data setup time
Parallel data hold time
Parallel/Serial setup time
Parallel/Serial hold time
Digital register delay
(internal)
Digital register delay
(internal, direct mode only)
DIH
PSIH
VALID
Parameter
T
PD
A
< 85° C, unless otherwise specified
Min
100
100
100
100
30
-
-
Max
Page 7 of 11
10
5
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns