MAX2390ETI+ Maxim Integrated Products, MAX2390ETI+ Datasheet - Page 6

• Manufacturer Part Number: MAX2390ETI+
• Description: RF Receiver IC RECEIVERS ZERO-IF-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX2390ETI+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC ELECTRICAL CHARACTERISTICS (continued)
(Devices tested on their respective evaluation kits (EV kits); LNA input port is driven with a 50Ω source; LNA output port is terminated
with 50Ω load, mixer differential input port is driven through a 1:4 impedance balun with a 50Ω source; baseband I/Q output differential
load = 10kΩ || 5pF; reference oscillator input: 19.2MHz (MAX2390/MAX2391/MAX2392/MAX2393), 26MHz (MAX2401), 15.36MHz
(MAX2396/MAX2400); AGC is set to result in a 0.3V
power-up defaults
W-CDMA/W-TDD/TD-SCDMA Zero-IF Receivers
6
Note 1: Logic thresholds track V
Note 2: All min and max specifications are measured over this frequency range.
Note 3: Guaranteed by design and characterization.
ON-CHIP VCO
VCO Frequency
(VCO Range is 2x the LO Range)
Phase Noise
Pulling
Pushing
VCO INTERFACE TO EXTERNAL SYNTHESIZER (MAX2396/MAX2400)
VCO Tuning Gain
VCO Output Frequency
VCO Output Differential Voltage
VCO Tuning Voltage Range
INTEGER-N RF SYNTHESIZER (MAX2390–MAX2393, MAX2401)
Main PLL Integer Division Ratio
Reference Frequency Range
REFDIV Reference-Divider Ratio
Charge-Pump Output Current
(Sink or Source)
Charge-Pump Leakage Current
SYSTEM TIMING
Turn-On Time Including
DC Offset Cancellation
3-WIRE SERIAL INTERFACE TIMING
Data to Clock Setup
Data to Clock Hold Time
Clock Pulse-Width High
Clock Pulse-Width Low
Clock to Load Enable/Setup Time
Clock Frequency
_______________________________________________________________________________________
PARAMETER
(Table
2); T
A
= -40°C to +85°C. Typical values are for V
SHDN
SYMBOL
V
K
I
t
f
t
f
L_CP
TUNE
CWH
. This allows the digital interface to operate with logic levels from 1.2V to V
OSC
ΦN
t
t
CWL
I
t
REF
t
VCO
ON
CH
CP
CS
ES
MAX2391/MAX2396
MAX2392
MAX2393
MAX2390/MAX2400
MAX2401
At 10MHz offset; locked (Note 3)
From IDLE mode to ON mode (Note 3)
V
Refer r ed to the V C O
fr eq uency ( 2x RFLO)
Output to synthesizer is
f
(Note 12)
15- b i t r eg i ster ( 64/65 d ual - m od ul us p r escal er ) ,
f
9-bit register
CONFIG:CP1 = 1, CONFIG:CP0 = 1,
V
From IDLE mode to ON mode VGA set to
maximum gain with -40dBm signal at
demodulator input (Note 3)
Per timing diagram
Per timing diagram
Per timing diagram
Per timing diagram
Per timing diagram
VCO
C OM P
CC
CPOUT
P-P
stepped 3.3V to 2.7V (Note 3)
/ 3 = 2f
= 200kH z
differential output-voltage swing at the baseband I/Q output; registers set to
= V
CC
RFLO
/ 2
CONDITIONS
/ 3
CC
M AX 2396
M AX 2400
MAX2396
MAX2400
= 2.8V and T
A
= +25°C, unless otherwise noted.)
1406.67 1426.67 1446.67
1286.67 1306.67 1326.67
4220
4020
3800
3860
3610
4032
MIN
130
100
180
0.4
2.0
10
16
20
10
20
20
20
10700
-139
TYP
19.2
0.5
2.5
96
30
CC
32767
MAX
4340
4050
3840
3980
3760
-133
.
300
270
511
2.3
3.0
13
40
10
60
20
1
MHz
dBc/Hz
UNITS
MHz/V
MHz/V
mV
MHz
MHz
MHz
MHz
mA
nA
µs
ns
ns
ns
ns
ns
V
P-P
P-P