MAX11008EVC16 Maxim Integrated Products, MAX11008EVC16 Datasheet
MAX11008EVC16
Specifications of MAX11008EVC16
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MAX11008EVC16 Summary of contents
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... Transmitters Industrial Process Control SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Nonvolatile Memory ♦ On-Chip 4Kb EEPROM for Storing LDMOS Bias Characteristics ♦ ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory ABSOLUTE MAXIMUM RATINGS AV to AGND .........................................................-0. DGND.........................................................-0.3V to +6V DD AGND to DGND.....................................................-0.3V to +0.3V CS_+, CS_- to AGND .............................................-0.3V to +34V CS_+ to CS_- If ...
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Dual RF LDMOS Bias Controller with ELECTRICAL CHARACTERISTICS (continued +32V +5V ±5%, external V CS_ -40°C to +85°C, unless otherwise noted. Typical values are ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory ELECTRICAL CHARACTERISTICS (continued +32V +5V ±5%, external V CS_ -40°C to +85°C, unless otherwise noted. Typical ...
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Dual RF LDMOS Bias Controller with ELECTRICAL CHARACTERISTICS (continued +32V +5V ±5%, external V CS_ -40°C to +85°C, unless otherwise noted. Typical values are ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory SPI TIMING CHARACTERISTICS (Notes 14, 15, Figure 1) (DV = +2.7V to +5.25V +4.75V to +5.25V 0.1µ -40°C to +85°C, unless otherwise noted.) ...
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Dual RF LDMOS Bias Controller with HIGH-SPEED-MODE TIMING CHARACTERISTICS (Notes 14, 15, Figure 4) (DV = +2.7V to +5.25V +4.75V to +5.25V 0.1µ -40°C to +85°C, unless otherwise ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory MISCELLANEOUS TIMING CHARACTERISTICS (Note 15) (continued) (DV = +2.7V to +5.25V +4.75V to +5.25V 0.1µ -40°C to +85°C, unless otherwise noted.) REF A ...
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Dual RF LDMOS Bias Controller with ( 5V, external V = 2.5V, external REFADC erwise noted.) ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE 2. INT REF AND DACS TURNED ON 2.09 ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory ( 5V, external REFADC erwise noted.) CURRENT-SENSE TRANSIENT RESPONSE ( MAX11008 toc10 V 1V/div 0V V 1V/div 0V 2µs/div GATE VOLTAGE TOTAL UNADJUSTED ERROR ...
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Dual RF LDMOS Bias Controller with ( 5V, external REFADC erwise noted.) ADC INTEGRAL NONLINEARITY vs. OUTPUT CODE 1.00 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 0 1024 2048 3072 4096 OUTPUT CODE ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory ( 5V, external V = 2.5V, external REFADC erwise noted.) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 2.52 2.51 V REFADC 2.50 V REFDAC 2.49 2.48 -50 -25 ...
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Dual RF LDMOS Bias Controller with PIN NAME 1, 31 DGND Digital Ground. Connect both DGND inputs to the same potential. Output Safe Switch Logic Input 1. Drive OPSAFE1 high to close the output safe switch and clamp 2 OPSAFE1 ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory A2/N.C. SCL/SCLK SERIAL INTERFACE SDA/DIN SPI/I2C FIFO EEPROM ALARM BUSY REFDAC REFADC 14 14 ______________________________________________________________________________________ ______________________________________________________________________________________ A1/DOUT A0/CS DV PGAOUT1 DD MAX11008 12-BIT DAC1 REGISTER MAP AND DIGITAL CONTROL 12-BIT DAC 2 ...
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Dual RF LDMOS Bias Controller with 4.7kΩ 4.7kΩ 5V SCL/SCLK SDA/DIN A0/CS A1/DOUT A2/N.C. µC OPSAFE1 OPSAFE2 ALARM BUSY CNVST SPI/I2C REFADC EXTERNAL 2.5V REFERENCE REFDAC 0.1µF 0.1µF PGAOUT1 PGAOUT2 ADCIN1 ADCIN2 *SDA RESISTOR VALUE VARIES WITH LOAD AND SCL ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory 5V µ EXTERNAL 2.5V REFERENCE 0.1µF 0.1µF *SELECT R LIMIT R 16 ______________________________________________________________________________________ Typical Application Circuits—SPI Interface 0.1µ SCL/SCLK SDA/DIN A0/CS A1/DOUT ...
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Dual RF LDMOS Bias Controller with Detailed Description The MAX11008 sets and controls the bias conditions for dual RF LDMOS power devices found in cellular base-station power amps. Each device includes two high-side current-sense amplifiers with programmable gains of 2, ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory The SPI bus cycles are 24 bits long. Data can be sup- plied as three 8-bit bytes continuous 24-bit stream. CS must remain low throughout the 24-bit sequence. The ...
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Dual RF LDMOS Bias Controller with Use the following sequence to read 16 bits of data from a MAX11008 register (see Figure 3): 1) Drive CS low to select the device. 2) Send the appropriate read command byte (see Table ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory A master device communicates to the MAX11008 by transmitting the proper slave address followed by a command and/or data words. Each transmit sequence is framed by a START (S) or repeated START ...
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Dual RF LDMOS Bias Controller with A bus master initiates communication with a slave device by issuing a START condition followed by the 7- bit slave address and a read/write (R/W) bit (see Figure 7). When the device recognizes its ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory MAX11008 returns to F/S mode. Use a repeated START condition in place of a STOP condition to leave the bus active and the mode unchanged. Figure 9 summarizes the data bit transfer ...
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Dual RF LDMOS Bias Controller with Register Address/Data Bytes (5-Byte Read Cycle) A read cycle begins with the master issuing a START condition followed by a 7-bit address, (see Figure 5 and Table 1) and a write bit (R/W = ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory The MAX11008 12-bit ADC uses a SAR conversion technique and on-chip track-and-hold (T/H) circuitry to convert the PGA outputs (PGAOUT1 and PGAOUT2), temperature measurements, and single-ended auxiliary input voltages (ADCIN1 and ADCIN2) ...
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Dual RF LDMOS Bias Controller with ADC Transfer Functions Figure 13 shows the unipolar transfer function for non- temperature measurements, and Figure 14 shows the bipolar transfer function used for temperature measure- ments. Code transitions occur halfway between suc- cessive-integer ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory complete the ADC powers down, BUSY is pulled low, and the results for all of the selected channels are available in the FIFO. The duration of the BUSY pulse is additive, depending ...
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Dual RF LDMOS Bias Controller with For a PGAOUT conversion, set CNVST low for a mini- mum of 30µs or maximum of 40µs. The BUSY output goes high at the start of the CNVST pulse and the PGAOUT conversion result ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory Figure 16 shows the functional diagram of the MAX11008 DACs. Each DAC includes an input and output register. The input registers hold the result of the most recent write operation, and the ...
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Dual RF LDMOS Bias Controller with ADC and DAC References The MAX11008 provides an internal low-noise +2.5V reference for the ADCs, DACs and temperature sensor. When using the internal reference the REFDAC and REFADC inputs can either be left open ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory High-Side Current-Sense Amplifiers and PGAs The MAX11008 provides dual high-side current-sense and differential amplifier capability. The current-sense amplifiers provide 32V input common-mode range. Both CS_+ and CS_- must be ...
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Dual RF LDMOS Bias Controller with moves the data from the FIFO and writes it to the EEPROM. The MAX11008 remains in LUT streaming mode until the specified amount of data is written to the EEPROM. Set the internal watchdog ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory Figure 17. Software Flow Control Example (Pseudo Code) 32 ______________________________________________________________________________________ COUNT = 0 NO COUNT < MAX YES NO FLAG (FIFO_OVER_FLOW YES WRITE DATA TO FIFO COUNT = COUNT + ...
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Dual RF LDMOS Bias Controller with Figure 18. Hardware Flow Control Example (Pseudo Code) ______________________________________________________________________________________ Nonvolatile Memory COUNT = 0 NO COUNT < MAX YES NO ALARM = 1 YES WRITE DATA TO FIFO COUNT = COUNT + 1 EXIT ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory high until the current scan is complete and the ADC sequence halts. In single-conversion mode (CKSEL1, CKSEL0 = 11), the BUSY signal remains high until the ADC has completed the current conversion ...
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Dual RF LDMOS Bias Controller with (MEASUREMENT VALUE TEMPERATURE OR CURRENT) HIGH THRESHOLD BUILT-IN HYSTERESIS BUILT-IN HYSTERESIS LOW THRESHOLD ALARM OUTPUT COMPARATOR MODE (ACTIVE LOW) INTERRUPT MODE (ACTIVE LOW) ALARM FLAG REGISTER READ Figure 19. ALARM Output Signal Example—Alarm Thresholds ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory MEASUREMENT VALUE (TEMPERATURE OR CURRENT) HIGH THRESHOLD LOW THRESHOLD ALARM OUTPUT COMPARATOR MODE (ACTIVE LOW) INTERRUPT MODE (ACTIVE LOW) ALARM FLAG Figure 21. ALARM Output Signal Example—Alarm Thresholds Configured for Hysteresis Mode ...
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Dual RF LDMOS Bias Controller with CODE)/4096 GATE_ REFDAC = [ LUTTEMP{Temp} + REFDAC SET _ LUTAPC{APC})]/4096 where actual gate voltage. GATE_ V = factory-set DAC code ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory Table 4. EEPROM Address Map WORD ADDRESS BIN DEC 0000 0000 0 0000 0001 1 0000 0010 2 0000 0011 3 0000 0100 4 0000 0101 5 0000 0110 6 0000 0111 ...
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Dual RF LDMOS Bias Controller with Table 4. EEPROM Address Map (continued) WORD ADDRESS BIN DEC 0010 0000 32 0010 0001 33 0010 0010 34 0010 0011 35 0010 0100 36 0010 0101 37 0010 0110 38 0010 0111 39 ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory The MAX11008 features 4Kb of EEPROM capable of storing up to 256 16-bit data words. The first 64 data words of the EEPROM contain configuration data (see Table 4) while the remaining ...
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Dual RF LDMOS Bias Controller with quantities. But to avoid the possibility of mathematical overflow, the magnitude of the values should be limited to 12 bits (-4096 to +4095, which allows full movement over the range of the 12-bit DAC). ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory 4) The resulting LUT pointer value is bound-limited to ensure it fits within the corresponding LUT. Negative pointer values are limited to zero, and pointer values that extend beyond the range of ...
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Dual RF LDMOS Bias Controller with Table 5e. LUT Configuration Examples REGISTER CONFIGURATION 1 ENTRY (EXAMPLE) POFF = 010100 INT = 00 Temperature PSIZE = 01 LUT1 TSIZE = 010 SOT = 100 0x5054 POFF = 000000 INT = 00 ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory ADC sample = 495 hex << x indicates a logical shift left by x number of bits. >> x indicates a logical shift right by x number of bits. 1) LUT pointer ...
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Dual RF LDMOS Bias Controller with that is sent with the slave address (see the Register Address/Data Bytes (5-Byte Read Cycle) section). Tables describe each register in detail. Register Descriptions High Temperature Threshold Registers (TH1, TH2) The ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory Table 6. Register Address Map REGISTER Channel 1 High Temperature Threshold Channel 2 High Temperature Threshold Channel 1 Low Temperature Threshold Channel 2 Low Temperature Threshold Channel 1 High Current Threshold Channel ...
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Dual RF LDMOS Bias Controller with Set FIFOSTAT use the ALARM output to monitor the data flow of the FIFO while in LUT streaming mode or message mode. See the LUT Streaming Mode and Message Mode sections ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory Table 11. Hardware Configuration Register DATA BITS BIT NAME RESET STATE D15* T1AVGCTL D[14:12]* T1LIMIT[2:0] D11 FIFOSTAT D10 ADCMON D[9:8] PG2SET[1:0] D[7:6] PG1SET[1:0] D[5:4] CKSEL[1:0] D[3:2] ADCREF[1:0] D[1:0] DACREF[1: Don’t ...
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Dual RF LDMOS Bias Controller with Table 11c. PGA1 and PGA2 Gain Setting Bits (PG_SET[1:0]) PG_SET1 PG_SET0 Don’t care. Table 11d. Clock Mode and CNVST Bit (CKSEL[1:0]) CKSEL1 CKSEL0 Internally timed acquisitions ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory Set T_AVG enable the temperature averaging and filtering function for channel 1 and channel 2. The TSRC_ field in the SCFG register controls the source of the sample. Set ...
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Dual RF LDMOS Bias Controller with Alarm Hardware Configuration Register (ALMHCFIG) (Read/Write) Configure the hardware alarm functions with bits D[10:0] in the Alarm Hardware Configuration register (see Table 14). Bits D[15:11] are don’t-care bits. Set AVGMON write ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory Table 12. Alarm Software Configuration Register DATA BITS BIT NAME RESET STATE D[15:12] Unused D11* A2AVG D10* T2AVG D9* A1AVG D8* T1AVG D7 TALARM2 D6 TWIN2 D5 IALARM2 D4 IWIN2 D3 TALARM1 ...
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Dual RF LDMOS Bias Controller with Table 13. Software Configuration Register DATA BITS BIT NAME RESET STATE D15* T2AVGCTL D[14:12]* T2LIMIT[2:0] D11 LDAC2 D10 TCOMP2 D9 APCCOMP2 D8 TSRC2 D[7:6] APCSRC2[1:0] D5 LDAC1 D4 TCOMP1 D3 APCCOMP1 D2 TSRC1 D[1:0] ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory Table 13a. Channel 2 Averaging Equation (T2AVGCTL) D15 CHANNEL 2 AVERAGING EQUATION 0 Average = average + 1/16 difference. 1 Average = average + 1/4 difference. Table 13b. Channel 2 Difference Limiter ...
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Dual RF LDMOS Bias Controller with Table 13d Calculation Trigger Condition GATE SOFTWARE CONFIGURATION SETTINGS TCOMP_ = 1 APCCOMP_ = 1 APCSRC_1 = 0 APCSRC_0 = 0 TCOMP_ = 1 APCCOMP_ = 1 APCSRC_1 = 1 APCSRC_0 = ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory Table 14. Alarm Hardware Configuration Register DATA BITS BIT NAME RESET STATE D[15:11] Unused D10* AVGMON D9 INTEMP2 D8 ALMCOMP D[7:6] ALMHYST[1:0] ALMCLMP2[1:0 D[5:4] ALMCLMP1[1:0 D[3:2] D1 ALMPOL D0 ALMOPEN X = ...
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Dual RF LDMOS Bias Controller with Table 14b. Clamp-Mode Select Bits (ALMCLMP[1:0]) ALMCLMP1 ALMCLMP0 CLAMP MODE Clamp gate alarm with clear Clamp gate Table 15. VSET Registers DATA BITS BIT ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory FIFO (see the Message Mode section) so that the data words can be read out through the serial interface. In message mode the FIFO is eight deep, and does not overflow. In ...
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Dual RF LDMOS Bias Controller with Table 16c. Temperature Hysteresis Limit Register Bits TxHIST[3:0] FUNCTION 0000 1 LSB (1 degree). I.e., no hysteresis 0001 2 LSBs (1 degree) 0010 3 LSBs (3 degree) 0011 ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory Software Clear Register (SCLR) (Write Only) Write to the Software Clear register to clear the internal registers with a single write command (see Table 25). Bits D[15:7] are don’t-care bits. FULLRST and ...
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Dual RF LDMOS Bias Controller with FIFOEMP is set to 1 when the FIFO is empty. Once data is placed into the FIFO, FIFOEMP is set to 0. When in ADC monitoring mode, FIFOOVER is set to 1 when a ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory LOWI_ is set to 1 when the individual channel 1 and channel 2 current-sense measurements exceed the individual channel 1 and channel 2 low current thresh- old and returns to 0 after ...
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Dual RF LDMOS Bias Controller with Bypass the AV supply with a 0.1µF capacitor to DD AGND, and place the capacitor as physically close as possible to the AV input. Bypass the DV DD with a 0.1µF capacitor to DGND, ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory Table 24a. FIFO Read Channel Tags (TAG[3:0]) CHANNEL TAGS TAG3 TAG2 TAG1 TAG0 Internal temperature sensor measurement. ADCMON bit must be set Channel 1 ...
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Dual RF LDMOS Bias Controller with Table 26. Flag Register DATA BITS BIT NAME RESET STATE D[15:12] Reserved D11 ALUBUSY D10 RESTART D9 FIFOEMP D8 FIFOOVER D7 HIGHI2 D6 LOWI2 D5 HIGHT2 D4 LOWT2 D3 HIGHI1 D2 LOWI1 D1 HIGHT1 ...
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Dual RF LDMOS Bias Controller with Nonvolatile Memory Table 27. LUT Streaming Register DATA BITS BIT NAME RESET STATE D[15:8] LUTSL[7:0] D[7:0] LUTSA[7:0] Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from ...
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