ISPLSI 2064VE-135LT100I LATTICE SEMICONDUCTOR, ISPLSI 2064VE-135LT100I Datasheet - Page 14

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ISPLSI 2064VE-135LT100I

Manufacturer Part Number
ISPLSI 2064VE-135LT100I
Description
CPLD ispLSI® 2000VE Family 2K Gates 64 Macro Cells 135MHz EECMOS Technology 3.3V 100-Pin TQFP
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet

Specifications of ISPLSI 2064VE-135LT100I

Package
100TQFP
Family Name
ispLSI® 2000VE
Device System Gates
2000
Maximum Propagation Delay Time
10 ns
Number Of User I/os
64
Number Of Logic Blocks/elements
16
Typical Operating Supply Voltage
3.3 V
Maximum Operating Frequency
135 MHz
Operating Temperature
-40 to 85 °C
ispLSI 2064VE 100-Pin TQFP Pinout Diagram (0.5mm Lead Pitch/14.0 x 14.0mm Body Size)
Pin Configuration
TDI/IN 0
1. NC pins are not to be connected to any active signals, VCC or GND.
BSCAN
RESET
GOE 1
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
GND
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
VCC
1
1
1
1
NC
NC
NC
NC
Y0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
ispLSI 2064VE
Top View
14
Specifications ispLSI 2064VE
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 TQFP/2064VE
TCK/IN 3
NC
I/O 38
I/O 37
I/O 36
NC
I/O 35
I/O 34
I/O 33
I/O 32
NC
Y1
NC
VCC
GOE 0
GND
Y2
I/O 31
I/O 30
I/O 29
I/O 28
NC
I/O 27
I/O 26
I/O 25
1
1
1
1
1

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