BOXDP55SB Intel (CPU), BOXDP55SB Datasheet - Page 16

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BOXDP55SB

Manufacturer Part Number
BOXDP55SB
Description
Manufacturer
Intel (CPU)
Datasheet

Specifications of BOXDP55SB

Lead Free Status / RoHS Status
Supplier Unconfirmed
Intel Desktop Board DP55SB Technical Product Specification
1.5.1
16
Table 3 lists the supported DIMM configurations.
Table 3. Supported Memory Configurations
Note:
The Intel Core i7 and Intel Core i5 processors supports the following types of memory
organization:
DIMM
Capacity
1024 MB
2048 MB
2048 MB
4096 MB
For information about…
Tested Memory
XMP Tested Memory
For information about…
Memory Configuration Examples
Dual channel (Interleaved) mode. This mode offers the highest throughput for
real world applications. Dual channel mode is enabled when the installed memory
capacities of both DIMM channels are equal. Technology and device width can vary
from one channel to the other but the installed memory capacity for each channel
must be equal. If different speed DIMMs are used between channels, the slowest
memory timing will be used.
Single channel (Asymmetric) mode. This mode is equivalent to single channel
bandwidth operation for real world applications. This mode is used when only a
single DIMM is installed or the memory capacities are unequal. Technology and
device width can vary from one channel to the other. If different speed DIMMs are
used between channels, the slowest memory timing will be used.
“DS” refers to double-sided memory modules (containing two rows of SDRAM) and “SS” refers to
single-sided memory modules (containing one row of SDRAM).
Memory Configurations
Configuration
(Note)
SS
DS
SS
DS
SDRAM
Density
1 Gbit
1 Gbit
2 Gbit
2 Gbit
Refer to:
http://support.intel.com/support/motherboards/desktop/sb/CS-
025414.htm
http://www.intel.com/personal/gaming/extremememory.htm
Refer to:
http://www.intel.com/support/motherboards/desktop/sb/cs-
011965.htm
SDRAM Organization
Front-side/Back-side
128 M x 8/empty
128 M x 8/128 M x 8
256 M x 8/empty
256 M x8/256 M x 8
Number of SDRAM
Devices
8
16
8
16