R0E572850CFK00 Renesas Electronics America, R0E572850CFK00 Datasheet - Page 48

• Manufacturer Part Number: R0E572850CFK00
• Manufacturer: Renesas Electronics America

Specifications of R0E572850CFK00

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Rev. 4.00 Feb. 18, 2009 Page 40 of 64
REJ10J1662-0400
6. If a condition of which intervals are satisfied closely is set, no sequential condition will
7. If the settings of the Event condition or the sequential conditions are changed during
8. If the settings of Event conditions or the sequential conditions are changed during
9. If the break condition before executing an instruction is set to the instruction followed
10. If the break conditions before and after executing instructions are set to the same
11. Do not set the break condition after executing instructions and BREAKPOINT
12. When the emulator is being connected, the user break controller (UBC) function is not
be satisfied.
• Set the Event conditions, which are satisfied closely, by the program counter with
• After the Event condition has been matched by accessing data, set the event
execution of the program, execution will be suspended. (The number of clock cycles to
be suspended during execution of the program is a maximum of about 102 bus clock
cycles (Bφ). If the bus clock (Bφ) is 20 MHz, the program will be suspended for 5.1
μs.)
execution of the program, the emulator temporarily disables all Event conditions to
change the settings. During this period, no Event conditions will be satisfied.
by DIVU and DIVS, the factor for halting a break will be incorrect under the following
condition:
If a break occurs during execution of the above DIVU and DIVS instructions, the break
condition before executing an instruction, which has been set to the next instruction,
may be displayed as the factor for halting a break.
address, the factor for halting a break will be incorrectly displayed. The factor for
halting a break due to the break condition after executing an instruction will be
displayed even if a break is halted by the break condition before executing an
instruction.
(software break) to the same address.
available.
intervals of two or more instructions.
condition by the program counter with intervals of 17 or more instructions.