89HPES4T4ZBBCGI Integrated Device Technology (Idt), 89HPES4T4ZBBCGI Datasheet - Page 5

• Manufacturer Part Number: 89HPES4T4ZBBCGI
• Description: PCI Express Switch 144-Pin CABGA Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 89HPES4T4ZBBCGI

• Package: 144CABGA
• Operating Temperature: -40 to 85 °C

IDT 89HPES4T4 Data Sheet
JTAG_TRST_N
SWMODE[2:0]
JTAG_TCK
JTAG_TDO
JTAG_TMS
JTAG_TDI
V
RSTHALT
Signal
Signal
Signal
V
WAKEN
DD
V
V
V
DD
DD
DD
TT
V
CORE
SS
APE
PE
I/O
PE
Type
I/O
Type
Type
I
I
O
I
I
I
I
I
I
I
I
I
I
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, the PES4T4 executes the reset procedure and remains in a reset
state with the Master SMBus active. This allows software to read and write
registers internal to the device before normal device operation begins. The
device exits the reset state when the RSTHALT bit is cleared in the
PA_SWCTL register by the SMBus master.
Switch Mode. These configuration pins determine the PES4T4 switch
operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0xF Reserved
Wake Input/Output. The WAKEN signal is an input or output. The WAKEN
signal input/output selection can be made through WAKEDIR bit setting in
the WAKEUPCNTL register.
Table 4 System Pins (Part 2 of 2)
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Core VDD. Power supply for core logic.
I/O VDD. LVTTL I/O buffer power supply.
PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
PCI Express Termination Power.
Ground.
Table 6 Power and Ground Pins
Table 5 Test Pins
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Name/Description
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January 25, 2011