83052AGI-01LF Integrated Device Technology (Idt), 83052AGI-01LF Datasheet - Page 6

• Manufacturer Part Number: 83052AGI-01LF
• Description: Clock Multiplexer 2-IN LVCMOS/LVTTL 16-Pin TSSOP Tube
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 83052AGI-01LF

• Package: 16TSSOP
• Configuration: 2 x 2:1
• Input Signal Type: LVCMOS|LVTTL
• Maximum Output Frequency: 250 MHz
• Operating Supply Voltage: 2.5|3.3 V

Table 5C. AC Characteristics, V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions
NOTE 1: Measured from the V
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same input on each device, the output is measured at V
NOTE 5: Driving only one input clock.
Table 5D. AC Characteristics, V
NOTE: See Notes above.
IDT™ / ICS™ SINGLE-ENDED MULTIPLEXER
Symbol
f
tp
tp
tsk(i)
tsk(o)
tsk(pp)
tjit
t
odc
MUX
Symbol
f
tp
tp
tsk(i)
tsk(o)
tsk(pp)
tjit
t
odc
MUX
MAX
R
MAX
R
ICS83052I-01
2-BIT, 2:1, SINGLE-ENDED MULTIPLEXER
LH
HL
LH
HL
/ t
/ t
F
F
ISOL
ISOL
Parameter
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Input Skew; NOTE 2
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 2, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
section, NOTE 5
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
Parameter
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Input Skew; NOTE 2
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 2, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
section, NOTE 5
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
DD
/2 of the input to V
DD
DD
= 3.3V ± 5%, V
= V
DDO
= 2.5V ± 5%, T
Integration Range: 12kHz - 20MHz
Integration Range: 12kHz - 20MHz
Unselected CLK input @100MHz
Unselected CLK input @100MHz
DDO
/2 of the output.
DDO
Test Conditions
Test Conditions
f
OUT
20% to 80%
20% to 80%
= 1.8V ± 0.2V, T
< 200MHz
A
DDO
=-40°C to 85°C
6
/2.
A
=-40°C to 85°C
Minimum
Minimum
200
2.0
2.0
150
40
2.2
2.2
40
ICS83052AGI-01 REV. A MARCH 9, 2009
Typical
Typical
0.19
0.14
2.7
2.7
15
45
3.1
3.1
20
15
30
45
Maximum
Maximum
1000
100
600
250
500
250
500
4.0
4.0
3.4
3.4
DDO
60
60
55
75
60
/2.
Units
Units
MHz
MHz
dB
dB
ns
ns
ps
ps
ps
ps
ps
ns
ns
ps
ps
ps
ps
ps
%
%