MT46V32M16BN-5B:F Micron Technology Inc, MT46V32M16BN-5B:F Datasheet - Page 65
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MT46V32M16BN-5B:F
Manufacturer Part Number
MT46V32M16BN-5B:F
Description
DRAM Chip DDR SDRAM 512M-Bit 32Mx16 2.6V 60-Pin FBGA Tray
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V32M16P-5BF_TR.pdf
(91 pages)
Specifications of MT46V32M16BN-5B:F
Density
512 Mb
Maximum Clock Rate
400 MHz
Package
60FBGA
Address Bus Width
15 Bit
Operating Supply Voltage
2.6 V
Maximum Random Access Time
0.7 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
512M (32Mx16)
Speed
5ns
Interface
Parallel
Voltage - Supply
2.5 V ~ 2.7 V
Package / Case
60-FBGA
Organization
32Mx16
Address Bus
15b
Access Time (max)
700ps
Operating Supply Voltage (typ)
2.6V
Package Type
FBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.5V
Supply Current
215mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT46V32M16BN-5B:F
Manufacturer:
MICRON
Quantity:
21
Company:
Part Number:
MT46V32M16BN-5B:F
Manufacturer:
MICRON
Quantity:
513
Company:
Part Number:
MT46V32M16BN-5B:F
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Company:
Part Number:
MT46V32M16BN-5B:F TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 30:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
Command
Command
Command
Address
Address
Address
Random READ Accesses
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
Notes:
Bank,
READ
Col n
READ
READ
Bank,
Bank,
Col n
Col n
T0
T0
T0
1. DO n (or x or b or g) = data-out from column n (or column x or column b or column g).
2. BL = 2, BL = 4, or BL = 8 (if BL = 4 or BL = 8, the following burst interrupts the previous).
3. n', x', b', or g' indicate the next data-out following DO n, DO x, DO b, or DO g, respectively.
4. READs are to an active row in any bank.
5. Shown with nominal
CL = 2
Bank,
Col x
Bank,
READ
READ
READ
Bank,
Col x
Col x
T1
T1
T1
CL = 2.5
CL = 3
T2
t
AC,
Bank,
Col b
READ
READ
READ
Bank,
Bank,
Col b
Col b
T2n
T2
T2
t
DQSCK, and
DO
65
n
T2n
T3
DO
DO
n'
n
Bank,
Col g
Bank,
Col g
T3n
READ
READ
Bank,
READ
Col g
T3
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSQ.
DO
DO
DO
n'
n
x
T3n
T3n
T4
512Mb: x4, x8, x16 DDR SDRAM
Transitioning Data
DO
DO
DO
n'
x'
x
T4n
T4
NOP
T4
NOP
NOP
DO
DO
DO
x
x'
b
T4n
T4n
T5
DO
x'
DO
DO
b'
©2000 Micron Technology, Inc. All rights reserved.
b
T5n
T5
T5
NOP
NOP
NOP
DO
Don’t Care
DO
DO
b'
b
g
T5n
T5n
DO
Operations
b'