XC2V1500-5FG676C Xilinx Inc, XC2V1500-5FG676C Datasheet - Page 92

• Manufacturer Part Number: XC2V1500-5FG676C
• Description: FPGA Virtex-II™ Family 1.5M Gates 17280 Cells 750MHz 0.15um/0.12um (CMOS) Technology 1.5V 676-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC2V1500-5FG676C

• Package: 676FBGA
• Family Name: Virtex-II™
• Device Logic Units: 17280
• Device System Gates: 1500000
• Number Of Registers: 15360
• Maximum Internal Frequency: 750 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 392
• Ram Bits: 884736

Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Virtex-II Data Sheet
The Virtex-II Data Sheet contains the following modules:
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DS031-3 (v3.5) November 5, 2007
Product Specification
03/01/05
11/05/07
(cont’d)
Virtex-II Platform FPGAs: Introduction and Overview
(Module 1)
Virtex-II Platform FPGAs: Functional Description
(Module 2)
Date
R
Version
(cont’d)
3.4
3.5
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•
•
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Table
include descriptions, as well as the actual IOSTANDARD attributes (used in Xilinx
ISE™ software) for all I/O standards.
Table
SSTL18_I_DCI, SSTL18_II_DCI, HSTL_I_18, HSTL_II_18, HSTL_III_18,
HSTL_IV_18, LVDSEXT_25, LVDSEXT_33, BLVDS_25, LVDS_25_DCI,
LVDS_33_DCI, LVDSEXT_25_DCI, LVDSEXT_33_DCI, HSLVDCI_15, HSLVDCI_18,
HSLVDCI_25, HSLVDCI_33. Rearranged I/O standards in a more logical order.
Table
Table
SSTL18_I_DCI, SSTL18_II_DCI, HSLVDCI_15, HSLVDCI_18, HSLVDCI_25,
HSLVDCI_33. Changed “Csl” to “C
Rearranged I/O standards in a more logical order.
Table
HSTL_I_18, HSTL_II_18, HSTL_III_18, HSTL_IV_18. Added footnote defining
equivalents for DCI standards.
Table
Added HSLVDCI callouts to LVDCI parameter rows (same values).
Table
Table
F
Table
Updated copyright notice and legal disclaimer.
CC_STARTUP
15,
15: Added data for the following I/O standards: SSTL18_I, SSTL18_II,
16: Added parameter T
17: Added data for the following I/O standards: SSTL18_I, SSTL18_II,
18: Added data for the following I/O standards: SSTL18_I, SSTL18_II,
19: Added Footnotes (2) and (3) to PCI/PCI-X capacitive load (C
28: Added parameter T
31: Added Footnote (1) indicating that F
33: T
Table
TCKTDO
if no provision is made to adjust the speed of CCLK.
17,
www.xilinx.com
corrected from a “Min” to a “Max” specification.
Table
Virtex-II Platform FPGAs: DC and Switching Characteristics
18, and
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RPW
BCCS
Virtex-II Platform FPGAs: DC and Switching
Characteristics (Module 3)
Virtex-II Platform FPGAs: Pinout Information
(Module 4)
Table
(Minimum Pulse Width, SR Input).
, CLKA to CLKB Setup Time.
REF
Revision
” to agree with
19: Restructured these I/O-related tables to
CC_SERIAL
Figure 1
should not exceed
and
Table
REF
19.
) values.
Module 3 of 4
(“CRITICAL
44