XC3S250E-4VQG100C Xilinx Inc, XC3S250E-4VQG100C Datasheet - Page 150

• Manufacturer Part Number: XC3S250E-4VQG100C
• Description: FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 100-Pin VTQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4VQG100C

• Package: 100VTQFP
• Family Name: Spartan®-3E
• Device Logic Cells: 5508
• Device Logic Units: 612
• Device System Gates: 250000
• Number Of Registers: 4896
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 66
• Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Total Ram Bits: 221184
• Number Of I /o: 66
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1525

DC and Switching Characteristics
Configuration and JTAG Timing
General Configuration Power-On/Reconfigure Timing
Table 111: Power-On Timing and the Beginning of Configuration
150
Notes:
1.
2.
3.
T
T
T
T
T
POR
PROG
PL
INIT
ICCK
(2)
The numbers in this table are based on the operating conditions set forth in
and V
Power-on reset and the clearing of configuration memory occurs during this period.
This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes.
(2)
Symbol
(3)
Notes:
1.
2.
3.
V
CCAUX
(Open-Drain)
CCO
The V
The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
PROG_B
V
(Supply)
(Supply)
(Supply)
(Output)
V
Bank 2
CCAUX
lines.
(Input)
INIT_B
CCINT
CCLK
CCINT
The time from the application of V
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
The width of the low-going pulse on the PROG_B pin
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
Minimum Low pulse width on INIT_B output
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
, V
Figure 74: Waveforms for Power-On and the Beginning of Configuration
CCAUX
, and V
CCO
supplies may be applied in any order.
Description
1.0V
2.0V
1.0V
CCINT
www.xilinx.com
T
T
POR
PROG
, V
CCAUX
, and V
Table
T
PL
CCO
77. This means power must be applied to all V
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
All
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
All
All
T
Device
ICCK
All Speed Grades
Min
250
0.5
0.5
DS312-3 (v3.8) August 26, 2009
-
-
-
-
-
-
-
-
-
-
DS312-3_01_103105
Product Specification
Max
0.5
0.5
4.0
5
5
5
5
7
1
2
2
-
-
1.2V
2.5V
CCINT
Units
, V
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
μs
ns
μs
CCO
,
R