XC3S5000-4FGG676I Xilinx Inc, XC3S5000-4FGG676I Datasheet - Page 91

FPGA Spartan®-3 Family 5M Gates 74880 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA

XC3S5000-4FGG676I

Manufacturer Part Number
XC3S5000-4FGG676I
Description
FPGA Spartan®-3 Family 5M Gates 74880 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet

Specifications of XC3S5000-4FGG676I

Package
676FBGA
Family Name
Spartan®-3
Device Logic Units
74880
Device System Gates
5000000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Ram Bits
1916928
Number Of Logic Elements/cells
74880
Number Of Labs/clbs
8320
Total Ram Bits
1916928
Number Of I /o
489
Number Of Gates
5000000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Miscellaneous DCM Timing
Table 63: Miscellaneous DCM Timing
DS099-3 (v2.5) December 4, 2009
Product Specification
98
Notes:
1.
2.
3.
4.
DCM_INPUT_CLOCK_STOP
DCM_RST_PW_MIN
DCM_RST_PW_MAX
DCM_CONFIG_LAG_TIME
These limits only apply to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and
CLKDV). The DCM DFS outputs (CLKFX, CLKFX180) are unaffected. Required due to effects of device cooling - see “Momentarily
Stopping CLKIN” in Chapter 3 of UG331.
Industrial-temperature applications that use the DLL in High-Frequency mode must use a continuous or increasing operating
frequency. The DLL under these conditions does not support reducing the operating frequency once establishing an initial operating
frequency.
This specification is equivalent to the Virtex-4 FPGA DCM_RESET specification.
This specification is equivalent to the Virtex-4 FPGA TCONFIG specification.
Symbol
R
(3)
(4)
Maximum duration that the CLKIN and
CLKFB signals can be stopped
Minimum duration of a RST pulse width
Maximum duration of a RST pulse width
Maximum duration from V
FPGA configuration successfully completed
(DONE pin goes High) and clocks applied to
DCM DLL
(1, 2)
Spartan-3 FPGA Family: DC and Switching Characteristics
Description
www.xilinx.com
CCINT
(1, 2)
applied to
(1, 2)
Frequency
Mode
High
High
DLL
Low
Low
Any
Any
Commercial
Temperature Range
N/A
N/A
N/A
N/A
100
3
Industrial
N/A
N/A
100
10
10
3
seconds
seconds
minutes
minutes
CLKIN
cycles
Units
ms
91

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