XC5VLX50-2FF676I Xilinx Inc, XC5VLX50-2FF676I Datasheet - Page 367
![FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50-2FF676I
Manufacturer Part Number
XC5VLX50-2FF676I
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-2FF676I
Package
676FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
440
Ram Bits
1769472
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
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- Download datasheet (14Mb)
X-Ref Target - Figure 8-11
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
1001 0011
(Repeating
Pattern)
SERDES_MODE=MASTER
BITSLIP_ENABLE = TRUE
BITSLIP_ENABLE = TRUE
D
D
SERDES_MODE=SLAVE
SHIFTOUT1 SHIFTOUT2
Figure 8-11: Circuit Diagram for Bitslip Configuration in 1:8 SDR Mode
SHIFTIN1
ISERDES
ISERDES
(Master)
(Slave)
Figure 8-11
to TRUE. Two ISERDES modules are in a master-slave configuration for a data width of
eight.
Guidelines for Using the Bitslip Submodule
Set the BITSLIP_ENABLE attribute to TRUE. When BITSLIP_ENABLE is set to FALSE, the
Bitslip pin has no effect. In a master-slave configuration, the BITSLIP_ENABLE attribute in
both modules must be set to TRUE.
To invoke a Bitslip operation, the BITSLIP port must be asserted High for one CLKDIV
cycle. In SDR mode, Bitslip cannot be asserted for two consecutive CLKDIV cycles; Bitslip
must be deasserted for at least one CLKDIV cycle between two Bitslip assertions. In both
SDR and DDR mode, the total latency from when the ISERDES captures the asserted
Bitslip input to when the “bit-slipped” ISERDES outputs Q1–Q6 are sampled into the
FPGA logic by CLKDIV is two CLKDIV cycles.
IOB
SHIFTIN2
(Q7)Q3
(Q8)Q4
BITSLIP
BITSLIP
illustrates the ISERDES configured in 1:8 SDR mode with Bitslip_ENABLE set
Q1
Q2
Q3
Q4
Q5
Q6
Q1
Q2
Q5
Q6
Initial
www.xilinx.com
1
0
0
1
0
0
1
1
Bitslip
1st
1
1
0
0
1
0
0
1
Input Serial-to-Parallel Logic Resources (ISERDES)
Bitslip
2nd
1
1
1
0
0
1
0
0
Bitslip
3th
0
1
1
1
0
0
1
0
Bitslip
4th
0
0
1
1
1
0
0
1
Bitslip
5th
1
0
0
1
1
1
0
0
Bitslip
Bitslip signal from system
6th
0
1
0
0
1
1
1
0
Bitslip
7th
0
0
1
0
0
1
1
1
8th Bitslip
(Back to initial)
1
0
0
1
0
0
1
1
ug190_8_11_100307
367
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