IDT5T9306NLI IDT, Integrated Device Technology Inc, IDT5T9306NLI Datasheet - Page 7
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IDT5T9306NLI
Manufacturer Part Number
IDT5T9306NLI
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet
1.IDT5T9306NLI.pdf
(14 pages)
Specifications of IDT5T9306NLI
Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
1000MHz
Output Logic Level
LVDS
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (max)
2.7V
Package Type
VFQFPN
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Quiescent Current
240mA
Lead Free Status / RoHS Status
Not Compliant
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Skew Parameters
Propagation Delay
Output Gate Enable/Disable Delay
Power Down Timing
RMS Additive Phase Jitter
Output Rise/Fall Time
NOTES:
1. AC propagation measurements should not be taken within the first 100 cycles of startup.
2. Skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device.
3. Skew measured is the difference between propagation delay times t
4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices, given identical transitions and load conditions
5. All parameters are tested with a 50% input duty cycle.
6. Guaranteed by design but not production tested.
IDT
on any one device.
at identical V
Symbol
IDT5T9306
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II
t
™
t
t
PWRDN
t
PWRUP
t
SK
SK
SK
t
t
t
t
t
PLH
PHL
PGE
PGD
t
R
/ ICS
f
JIT
(
O
/t
(
(
PP
O
P
F
)
)
)
™
LVDS CLOCK BUFFER TERABUFFER™ II
DD
levels and temperature.
Parameter
Same Device Output Pin-to-Pin Skew
Pulse Skew
Part-to-Part Skew
Propagation Delay A, A Crosspoint to Qn, Qn Crosspoint
Frequency Range
Output Gate Enable Crossing V
Output Gate Disable Crossing V
PD Crossing V
Output Gate Disable Crossing V
RMS Additive Phase Jitter @ 25MHz (12kHz – 10MHz Integration Range)
RMS Additive Phase Jitter @ 125MHz (12kHz – 20MHz Integration Range)
RMS Additive Phase Jitter @ 156.25MHz (12kHz – 20MHz Integration Range)
Output Rise/Fall Time
(3)
THI
(4)
(6)
to Qn = V
(6)
, (20% - 80%)
DD
THI
, Qn = V
THI
THI
to Qn/Qn Crosspoint
to Qn/Qn Crosspoint Driven to GL Designated Level
to Qn/Qn Driven to GL Designated Level
PHL
(2)
and t
DD
PLH
of any differential output pair under identical input and output interfaces, transitions and load conditions
7
Min.
125
—
—
—
—
—
—
—
—
—
IDT5T9306 REV. B October 21, 2008
(1,5)
0.541
0.159
0.185
Typ.
1.25
—
—
—
—
—
—
—
—
Max
1.75
125
300
100
100
600
3.5
3.5
25
1
GHz
Unit
μS
μS
ps
ps
ps
ns
ns
ns
ps
ps
ps
ps