IDT854058AGLF IDT, Integrated Device Technology Inc, IDT854058AGLF Datasheet - Page 7

• Manufacturer Part Number: IDT854058AGLF
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Multiplexerr

Specifications of IDT854058AGLF

• Number Of Clock Inputs: 8
• Mode Of Operation: Differential
• Output Frequency: 2500MHz
• Output Logic Level: LVDS
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: CML/LVDS/LVPECL/SSTL
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Compliant

W
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
LVDS D
A general LVDS interface is shown in Figure 2. In a 100 differ-
ential transmission line environment, LVDS drivers require a
matched load termination of 100 across near the receiver in-
854058AG
IRING THE
RIVER
D
Integrated
Circuit
Systems, Inc.
IFFERENTIAL
T
ERMINATION
3.3V
I
F
NPUT TO
IGURE
LVDS_Driv er
Single Ended Clock Input
100 Ohm Differiential Transmission Line
1. S
F
A
IGURE
A
PPLICATION
www.icst.com/products/hiperclocks.html
CCEPT
INGLE
PRELIMINARY
2. T
E
C1
0.1u
S
YPICAL
NDED
V_REF
INGLE
DD
/2 is
S
LVDS D
IGNAL
E
D
7
I
NDED
IFFERENTIAL
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
put. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the un-used outputs.
NFORMATION
D
1K
R1
1K
R2
RIVING
RIVER
VDD
L
R1
100
EVELS
nPCLK
T
PCLK
D
ERMINATION
IFFERENTIAL
-
TO
-LVDS C
+
-
I
3.3V
NPUT
DD
= 3.3V, V_REF should be 1.25V
LOCK
ICS854058
REV. A OCTOBER 29, 2008
M
ULTIPLEXER
8:1